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As far as i understand turning off a MOSFET too fast, is bad, as high drain-source dv/dt can cause ringing through:
a) biasing Parasitic NPN and:
b) charging the GS capacitor through DG capacitor, and thus turning on the MOSFET.

1- is my understanding correct?
2- if yes, then it won't be an issue in the circuit below, which uses a diode to turn off the MOSFET as fast as possible?
3- is that diode even necessary, considering there is only one low side MOSFET, thus no chance of shoot-through?

enter image description here

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  • \$\begingroup\$ Also depends on the (unstated) load. Does that have an inductive component? Turning the MOSFET OFF too slowly is also problematic because the MOSFET dissipates power during this time. \$\endgroup\$ – Brian Drummond Jan 2 at 13:00
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Your understanding is correct. To break down the issues a bit more:

  1. Turning the MOSFET ON too fast can cause overshoot and ringing at the drain, hence the use of a low ohms resistor right at the gate. The ultra fast diode is to turn the MOSFET OFF faster than it turns ON, but the diode has internal resistance. What is bad is driving the gate with no resistor at all.

  2. Yes the diode can be removed for the reasons you mentioned-there is no 'competing' MOSFET. If this were a totem pole or push-pull design the diodes would help insure one is turning OFF before the other MOSFET turns on. This would include both sides of an H-Bridge topology.

  3. At high clock rates and wide pulse widths there is a risk of shoot-through for a totem pole design, or in a push-pull design the core can saturate and blow a fuse, or in a worst case scenario the ferrite core can crack.

EDIT: Not sure what you are looking for that is not already well documented. The MOSFET should always have a low value resistor right at the gate. Not only does it limit rise and fall times to prevent ringing and EMI emissions it prevents the gate from picking up stray RF which can modulate the drain current so that it is no longer producing a clean pulse of current.

As far as stray inductance goes that it usually due to poor layout. The driver IC, the MOSFET and the load should form a tight triangle with short fat traces for all leads except the one to the gate, which can be very narrow as long as it is short.

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  • \$\begingroup\$ Thanks. can you elaborate on the first part of your answer please? electronics.stackexchange.com/questions/414805/… \$\endgroup\$ – Sudoer Jan 2 at 9:51
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    \$\begingroup\$ Added EDIT section to cover more details. If you want the math and other esoteric details please read the thousands of articles on designing with MOSFETs. \$\endgroup\$ – Sparky256 Jan 2 at 16:10

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