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General question, how can I improve it? or make it more efficient? mabye there is something im missing...


  1. How can I deliver more dc voltage to the load? how do I improve my swing, im getting around 5.5volt
  2. How can I improve the voltage distortion when increasing voltage input?
  3. My phase is shifted in the output? tried to increase C7 didnt help.
  4. How to improve BW and CMRR?
  • 2
    \$\begingroup\$ This is the culmination of all of your previous questions. Did you learn nothing along the way? In any case, we discourage broad, open-ended design review questions here on EE.SE, because the answer(s) tend to become long strings of unrelated edits and/or comments. While this might help you with your immediate problems, it is of no value to the site overall. We DO allow design review questions in which you explain your choices and then focus on a few points about which you still have doubts. To get a better feel of what is or is not acceptable, search for "design review" on the meta site. \$\endgroup\$ – Dave Tweed Jan 2 at 15:42
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    \$\begingroup\$ I'd lightly bias those emitters (of Q2 and Q4) to +6volts; use two resistors, each of 10Kohms. By the way, with only one input, CMRR is meaningless. \$\endgroup\$ – analogsystemsrf Jan 2 at 16:02
  • \$\begingroup\$ Your bandwidth limitation is probably R29 and the Miller Input capacitance of that high-gain common-emitter stage. \$\endgroup\$ – analogsystemsrf Jan 2 at 16:05
  • \$\begingroup\$ Why isn't global NFB applied to \$Q_{11}\$?? \$\endgroup\$ – jonk Jan 2 at 19:07

Maybe something like this


simulate this circuit – Schematic created using CircuitLab

You have to decide if the entire amplifier (gain of 10,000) is viable.

1) Can the non-Darlington Q1/Q2 be a light enough load that Q5 (transconductor) and Q7 (stiff current source/load) will provide 100X gain?

2) can you achieve another gain of 100X in a diffpair, if the load is D1+R4

3) how to achieve negative feedback

4) how to generate a BODE plot, so you can examine the gain margin and the phase margin

5) how to compensate the entire amplifier, even if the load (not shown) happens to be a reactive (inductive, capacitive) loud speaker load of 16 ohms?

6) does the output swing around GROUND (so you need +- 12volts, or you need a large output DC_blocking cap (not shown))

7) how to bias the input?

8) is base of Q3, or of Q4, the input?

9) what is the low-end rolloff, if C2 and R9 set that highpass response?


If you use a resistive load on a common-emitter stage, the most gain you can get in one stage is VDD/0.026 volts. Thus 26volts allows a gain of 1,000. Your use of two gain stages, assuming resistive loads, seems reasonable, indeed mandatory.

But with current-source "active" loads, the gain can be much higher, limited by EarlyVoltage and/or the "hie" feedback from collector-to-base.

Something like this can produce massive gain in just one stage


simulate this circuit – Schematic created using CircuitLab

Probably need a BIG capacitor across R9, to get highest gain. And will not be precise gain.


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