I have started to wonder what is the significance of the timing simulation for FPGAs nowadays. I can easily justify what is the idea behind that by quoting some Xilinx materials:
Performing a thorough timing simulation ensures that the finished design is free of defects that can easily be missed, such as the following:
Post-synthesis and implementation functionality changes caused by the following: Synthesis attributes or constraints that can cause simulation/implementation mismatches, such as translate_off/translate_on or full_case/parallel case. UNISIM attributes applied in the UCF file or using synthesis attributes Differences between synthesis interpretation of language in different simulators
Dual-port RAM collisions
Missing or improperly applied timing constraints
Operation of asynchronous paths
Howevery, I do not know any engineers or companies in my area that would perform timing simulations for FPGAs. They just assume that if the timing constraints are correct and there are no timing violations after the place and route, then everything is fine.
I can understand this approach as timing simulation can take a lot of time for complex designs and, to be honest, I have never heard or read any story that timing simulation for FPGA has helped in fixing some bug that wouldn't be a bug on the functional level of the design.
Can we just say that nowadays timing verification of the FPGA designs has been reduced to trusting outputs of the vendors tool chains?