Tower Sawyer Circuit - High impendance DUT

I am trying to assemble a Tower-Sawyer circuit for measuring Ferroelectric loops. On a picture below you can see the most simple design of Tower-Sawyer circuit, with a parasitic capacitance in parallel to Sample.

simulate this circuit – Schematic created using CircuitLab

Function Gen - is a function generator which will be running sine frequencies from 20 Hz to 10 kHz and voltages from few mV to 1kV.

Oscilloscope Ch1 is the first channel of the oscilloscope which will measure the voltage of a Function Gen. It will be connected to a voltage divider which I didn't bother to drawing (because it is not a problem).

C sample - is the capacitance of the sample.

C parasite - is the parasitic capacitance that always comes with this setup (sample holder).

C ref - is the reference capacitor on which the second channel of an oscilloscope is connected. Due to the nature of the circuit, the reference capacitor must have capacitance that is much larger than C sample.

So the problem is as follows, I want to get rid of the contribution of C parasite (parasitic capacitance) that is in parallel with a sample. The current on the C ref (referent capacitor) should be only due to the sample. The nature of this parasitic capacitance is in the sample holder, coaxial cable and current contact setup i.e. it is difficult to reduce it without designing a new sample holder.

Question: Is it possible to "nullify" the parasitic capacitance with guarding, assuming high impedance C sample? If yes, do I need to find a buffer that can guard high voltages? Advice is welcome.

To be clear, I want to have almost zero current through C parasite.

P.s. It is probably evident but my background is not in electrical engineering ... sorry.

• I'm not familiar with the theory of measurement here, but is there a reason why you cannot just scale up both C_ref and C_sample so they are both significantly larger than the parasitic capacitance? – Justin Jan 3 at 21:56
• C_sample is not scalable. It is a material that i need to test if it is ferroelectric. About C_ref, i can scale it but if i can't change sample capacitance it does not do me any good. – zeljko Jan 3 at 22:03
• This sounds like the same type of problem as scope probe compensation (see electronics-notes.com/articles/test-methods/oscilloscope/…). The exact trim arrangement may need to be different since you are not just doing a simple resistive divider, but the same concepts should hopefully apply. Some simulation would be a good idea. – Justin Jan 4 at 2:24
• An easier option might just be to measure the parasitic capacitance (by using a known c_sample, perhaps), and just removing its effects from future measurements by calculation. – Justin Jan 4 at 2:27
• Why is C parasitic so large? 1m cable capacitance? – Sunnyskyguy EE75 Jan 4 at 3:19