I am trying to assemble a Tower-Sawyer circuit for measuring Ferroelectric loops. On a picture below you can see the most simple design of Tower-Sawyer circuit, with a parasitic capacitance in parallel to Sample.
Function Gen - is a function generator which will be running sine frequencies from 20 Hz to 10 kHz and voltages from few mV to 1kV.
Oscilloscope Ch1 is the first channel of the oscilloscope which will measure the voltage of a Function Gen. It will be connected to a voltage divider which I didn't bother to drawing (because it is not a problem).
C sample - is the capacitance of the sample.
C parasite - is the parasitic capacitance that always comes with this setup (sample holder).
C ref - is the reference capacitor on which the second channel of an oscilloscope is connected. Due to the nature of the circuit, the reference capacitor must have capacitance that is much larger than C sample.
So the problem is as follows, I want to get rid of the contribution of C parasite (parasitic capacitance) that is in parallel with a sample. The current on the C ref (referent capacitor) should be only due to the sample. The nature of this parasitic capacitance is in the sample holder, coaxial cable and current contact setup i.e. it is difficult to reduce it without designing a new sample holder.
Question: Is it possible to "nullify" the parasitic capacitance with guarding, assuming high impedance C sample? If yes, do I need to find a buffer that can guard high voltages? Advice is welcome.
To be clear, I want to have almost zero current through C parasite.
P.s. It is probably evident but my background is not in electrical engineering ... sorry.