Clock Domain Crossing

While reading the concept of CLOCK DOMAIN CROSSING I came across the 2 flip-flop synchronizer. If my first flop goes into metastable state, then how will it detect the correct value of data when it will come out of the metastable state? If my input is '1' and after coming out of metastable state my flip flop detects it as '0' then won't it create a problem in circuit as it is propagating false output through the whole circuit?

A chain of flip-flops does not 'cure' metastability. However, by delaying the final decision, it gives more time for the metastability to resolve itself, so reduces its likelihood. As the likelihood of it persisting falls exponentially as time passes, you do not have to add many stages for a circuit to improve enough to be usable.

To put some numbers on it. Let's say a flip flop has a metstability resolution time constant of 1nS, is operating at a 100MHz clock, and fails once per hour, needing a system reboot to recover from the resulting crash. If we add a second stage, then it improves things by 10 time constants, e^10, that is 22000, so now fails once in 2.5 years, a huge improvement, maybe good enough for some products. Add another stage and it fails once in 55000 years, probably good enough for one system to be called perfect. However, if you had deployed 10M systems to customers, then there would still still be 2 failures in the field per year. You do the sums for what improvement adding another stage would result in.

If a flip-flop goes metastable, it means it doesn't matter whether the output is 0 or 1, there is no 'correct' result, as long as two other circuits using the output data agree what it is. For instance, let's synchronise an external interrupt line to the program counter logic. Did an interrupt occur this clock cycle? If yes, provide the next program address from the interrupt vector. If no, provide it from the program counter. If the IV thinks there was no interrupt, and the PC thinks there was, then the system could crash.

See other answers 1 2 3 so I don't have to type too much more .

• Thank you Neil. How will I be able to know how many flipflops to connect in my design so that metastability gets resolved and system never fails? – Payal Jan 4 at 7:36
• You do the experiment. With only one flip-flop, you turn up the system clock rate until metastability becomes observable. Then you turn the clock rate up and down, and measure the metastability resolution time constant. Then you add just one more flip-flop and turn the clock up some more to verify your calculations. Then you have a think and decide what failure rate is tolerable for you. Then you choose a clock rate, and do the exponential sum to choose a number of flip-flops., and deploy that system. You can do a stress test where you time the input edge to be the worst possible timing. – Neil_UK Jan 4 at 7:43

If there is meta-stability, that directly implies that there was no “valid” value of data at the specific sample time. Thus both 0 and 1 were acceptable valid data values at that time.

What is now, at this particular moment in time, considered “valid” has nothing to do with the validity of the data when it was sampled.

The actual problem with metastability is that the output has not settled to a specific value in the allotted time, which can cause metastable and unpredictable signals to propagate down the chain, creating all sorts of logic hazards, unpredictable glitches and oscillations, and excess localized power dissipation.

Making a definitive decision about the data, any decision at all, in the allotted time, avoids these problems.

• Unfortunately, a 'definitive' decision cannot be made in any finite time. It's all about managing the probability of no decision being taken. – Neil_UK Jan 4 at 7:29