Problem in blocking and non-blocking - verilog

Question

I have this code and I am having a problem in the product output, any ideas? I've tried a lot and it doesn't work.

This is the full code:

// 32X32 Multiplier arithmetic unit template
module mult32x32_arith (
    output reg [63:0] product, // Miltiplication product

    // Multiplier controls
    input wire [31:0] a,        // Input a
    input wire [31:0] b,        // Input b
    input wire [1:0] a_sel,     // Select one byte from A
    input wire       b_sel,     // Select one 2-byte word from B
    input wire [5:0] shift_val, // Shift value of 8-bit mult product
    input wire upd_prod,        // Update the product register
    input wire clr_prod,        // Clear the product register
    input wire clk,             // Clock
    input wire rst              // Reset
);

// Put your code here
// ------------------

// Used registers 
reg [63:0] mult_prod;
reg [63:0] mult_prod_temp;

initial begin
 product = 0; 
 mult_prod = 0;
 mult_prod_temp = 0;
end

// mux outputs
reg [7:0] z1;
reg [15:0] z2;
reg [63:0] val;

// updating selector inputs
always @(a_sel or b_sel)
begin: test

case (a_sel)
2'b00: 
if(b_sel == 1'b0) begin
assign z1 = a[7:0];
assign  z2 = b[15:0];
end

else begin 
assign z1 = a[7:0];
assign  z2 = b[31:15];
end

2'b01:
if(b_sel == 1'b0) begin
assign z1 = a[15:8];
assign  z2 = b[15:0];
end

else begin 
assign z1 = a[15:8];
assign z2 = b[31:15];
end

2'b10: 
if(b_sel == 1'b0) begin
assign z1 = a[23:16];
assign z2 = b[15:0];
end

else begin 
assign z1 = a[23:16]; 
assign z2 = b[31:15]; 
end

2'b11: 
if(b_sel == 1'b0) begin
assign z1 = a[31:24];
assign z2 = b[15:0];
end

else begin 
assign z1 = a[31:24];
assign z2 = b[31:15];
end

endcase
end

always @(z1 or z2 or shift_val)
begin: Arithmetics

// 8x16 multiplier
 mult_prod_temp = z2*z1;

// Shifter
 mult_prod = (mult_prod_temp << shift_val);

// Output 
 val = (product + mult_prod);
 product <= val;
end


// End of your code
endmodule

I'm trying to implement a 32x32 multiplier using 8x16 multiplier, but I am having a problem in the output (product), it does not give me the right expected answer (check the attached photo below), and I'm trying to figure out where's the problem, whether it's in the syntax of the always procedure or somewhere else.

Thanks in advance!

Answer 1

I think it's because you have:

mult_prod = (mult_prod << shift_val);

Remember mult_prod is a bus, not a variable but a representation of a physical set of wires. An assignment like this implies that those wires simultaneously have two different states. Try introducing an intermediate term like mult_prod_temp, like:

// 8x16 multiplier
 **mult_prod_temp** = z2*z1;

// Shifter
 mult_prod = (**mult_prod_temp** << shift_val);

//output
val = (product + mult_prod);
product <= val;