This is what I've done so far and I really don't understand how to continue. The V variable is for verification
[EDIT]
it works for Y2 and Y0, but it doesn't work for Y1
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I'm not sure how to give you a hint without giving you the complete answer.
But consider the difference between these two situations:
- If any of the inputs to the upper encoder are asserted, then its outputs become the overall outputs, and Y2 needs to be asserted.
- If none of the inputs to the upper encoder are asserted, then the outputs of the lower encoder become the overall outputs, and Y2 needs to be negated.
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Connect Y0, Y1 to both 4:2 in parallel. Use Y0 as the 3rd "address" line and a NOT gate to enable one or the other.
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\$\begingroup\$ Not sure where you're going with this. It's actually the V output of the upper encoder that becomes the third Y output. And you also need to mux the two V together to create the overall V output. \$\endgroup\$ – Dave Tweed♦ Jan 4 at 17:51
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\$\begingroup\$ I see, so the desired result is turning say 1 only of I0 to I7 being High or Low into a 3-bit outcome? \$\endgroup\$ – CrossRoads Jan 4 at 18:04
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\$\begingroup\$ No, it's a priority encoder. Any combination of inputs can be asserted, and it's the topmost asserted input that gets encoded. \$\endgroup\$ – Dave Tweed♦ Jan 4 at 18:53
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\$\begingroup\$ Ok. Never had to design that functionality into any design I've done. \$\endgroup\$ – CrossRoads Jan 4 at 20:09
