I have searched for hours trying to find stack structures for cortex m and cortex a devices. I am attempting to add freertos debugging support for the cortex a5 to eclipse via the jlink SDK. The code for the jlink and the code for openocd are similar, and both show the same offsets for the cortex M, which show a non contiguous arrangement. All the data sheets I can find for the a5 and the M don’t show in what order these are pushed and popped into stack ram, but obviously the writers of that code found it somewhere. Perhaps I just don’t know what to google, or maybe I have a misunderstanding here, but where could I find this information?
This is defined in GDB, GCC and FreeRTOS rather than ARM. I had some misconceptions about how this worked, and really the stack info I needed was stored in the TCBstub/List pointer in the order specified by the port and the items being pushed onto the stack before context switching.
The order of the 'g' packet is defined by gcc/gdb and can be viewed by the command "maint print registers" from the gdb console.