1
\$\begingroup\$

This question is an exact duplicate of:

Apologies if the question is worded oddly/weirdly, but specifically I have a comparator with an unstable output which I know could be fixed with hysteresis, but I would rather just have some circuit output high indefinitely once the correct conditions are met and the comparator outputs high once. I know I could use a microcontroller and program it to keep track using memory, but I was just wondering if there was something simpler I could use. I'm still an electonics newbie, so any help/pointers/or even just the name of such a circuit would be much appreciated!

If it helps, I could go more in depth on what my circuit is/draw up a schematic, but I didn't want to drag this on for too long. Much thanks for reading this!

\$\endgroup\$

marked as duplicate by Dave Tweed Jan 5 at 15:14

This question was marked as an exact duplicate of an existing question.

  • 1
    \$\begingroup\$ This is a memory cell or latch a.k.a. "register". It can be state or level controlled input with a separate reset a.k.a. RS flip flip or it can be an edge sensitive D Flip Flop \$\endgroup\$ – Sunnyskyguy EE75 Jan 5 at 8:40
0
\$\begingroup\$

This is a good solution:

schematic

simulate this circuit – Schematic created using CircuitLab

Basically, once you give the input '1', the output of the OR gate will be '1'. Now, what you need to do is give the EN pin '1' so the DFF will detect a rising edge.

Once that is done, the output of the DFF, Q, will constantly output '1'.


Another solution, if you don't want to have two input signals, is to use a resistor-capacitor for time delay. Once your input goes high, after a while your clk/enable pin will go high as well, thus saving you the need for another input.

schematic

simulate this circuit

\$\endgroup\$
0
\$\begingroup\$

Use a rising edge re-settable D-flip-flop with the D connected high . Your signal goes into the clock input. If you have an active low reset you can use the standard R-C delay.

When a high (rising edge) comes into the clock pin the Q output becomes high and will stay that way until the register is reset.

The schematic below is a bit incomplete as I could not find a symbol for a D-register with reset.

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$
0
\$\begingroup\$

schematic

simulate this circuit – Schematic created using CircuitLab

This is a latch with logic =1 5V when Vin > Vref and stays there until a power cycle.

  • 90% Hysteresis (overkill) controlled by R1/(R1+R2)
  • R3 is just in case it is open collector comparator.

  • This is inverted to what you asked for so high is fault or over threshold.

  • If you swap the inputs for Vref and 0~Vin then it is inverting (low in= Hi ok out)
    • but then you want to swap R2,R1 values and threshold then R2/(R1+R2) * Vref
  • so with R1=10k and R2= 100k to have ~+-9% hysteresis. (1/11=9%)
\$\endgroup\$

Not the answer you're looking for? Browse other questions tagged or ask your own question.