This is a typical exam question, and I've seen some very helpful posts about, but I still have a lot of doubts.

Given an integrated circuit of certain dimensions, for this example a 4x2, I have to design a RAM memory with x addresses and y bits each. Here is an example of the circuit I have to use:

enter image description here

  • A0, A1 – address lines
  • D0, D1 – data lines
  • R/W – read/write line
  • CS – Chip Selection line

With IC1’s I’ll have to make a RAM memory with 8 addresses, 8 bits each, indicating the memory’s CS (Chip Selection) line.

So far what I can figure out from this is that IC1 has 4 cells, or addresses, and each one can hold 2 bits. So if I need 8 addresses that would mean I need to have 2 IC1's, but then they wouldn't hold enough bits, meaning that I need two more (using only the data pins)?

I'm very confused on how to make these designs, as I never had the chance to build any in a lab scenario. I hope someone can give me some hints or show me how these chips could be connect to make the desired memory. I'm not looking just for the answer to the example because I'll have to build other RAM's with different chips.

This is what I've come up with:

enter image description here

  • 1
    \$\begingroup\$ Distinguish between width expansion and depth expansion each is independent of the other and requires a separate approach. \$\endgroup\$
    – Oldfart
    Jan 5, 2019 at 16:27
  • \$\begingroup\$ The AND gates you've drawn in are backwards, and don't make any sense. \$\endgroup\$
    – user39382
    Jan 6, 2019 at 21:31
  • \$\begingroup\$ Yes, I knew that couldn't be right @duskwuff but I just can't figure out how to negate one of the banks. If I could use two chips to do this I'd just have to use a inverter before connecting the CS line to one of them. I've update my draft. \$\endgroup\$ Jan 7, 2019 at 17:25
  • \$\begingroup\$ You've left this half-completed. If you finish it, the correct answer will be useful to other site users. \$\endgroup\$
    – TonyM
    Jan 10, 2019 at 18:06
  • 1
    \$\begingroup\$ As promised @TonyM , I've posted an answer of my own with what I think is the correct way to negate de upper bank, hope I nailed it this time. \$\endgroup\$ Jan 18, 2019 at 13:59

2 Answers 2


You need two banks of four chips. The four chips in each bank simply have their A0, A1, CS, R/W signals connected and their D0/D1 connected to D0/D1, D2/D3, D4/D5, D6/D7.

The CS signal of each bank has to be calculated by a logic using the external CS and the external A2 signal. Two AND gates and one inverter.

These are all pointers you need.

  • \$\begingroup\$ Thank you for the tips, I've added my draft to the question. Am I forced to use AND's and the inverter to do achieve what I want, or is it just a matter of being more organized? \$\endgroup\$ Jan 6, 2019 at 14:28
  • \$\begingroup\$ Your draft is missing the A2 logic. You need some means to generate the CS signal for the upper vs. the lower bank. Only one of them may be active when outer CS is active. That is done with the two AND gates and the single inverter. \$\endgroup\$
    – Janka
    Jan 6, 2019 at 14:59
  • \$\begingroup\$ Thanks for bearing with me so far @Janka , I've updated my draft, but I feel like I didn't use the AND gates correctly. I'm begining to understand this, I'm just unsure on how the connection and invertion is made between multiple banks. If I had to use only two chips all I had to was make the invertion before connecting to the CS of one of them. \$\endgroup\$ Jan 6, 2019 at 19:15
  • \$\begingroup\$ You should revisit how AND gates function first. Then, remember you have to feed the external CS and A2 signals into them, and get the internal upper CS and lower CS as a result. \$\endgroup\$
    – Janka
    Jan 6, 2019 at 22:34
  • 1
    \$\begingroup\$ @BlindRoach, you are now so close with only the address decoder to do, as you've probably realised. This is best solved by drawing a truth table - it'll let you see clearly what the decoder should do. You can solve it all from here, whole circuit. Draw a truth table with inputs (CS, A2) and outputs (selLoBank, selHiBank) then populate it with what you need it to do. Only then should you think about your AND and NOT gates. Keep going :-) \$\endgroup\$
    – TonyM
    Jan 7, 2019 at 17:26

After all the tips everyone gave me, and brushing up on circuit building, this is what I've come up with.

enter image description here

I see now what was wrong with all my other drafts, as I still wasn't too sure on how the CS operated. To be sure that I understood this, I've made another memory, this time a 4x2 using 2x1s. Here is my solution:

enter image description here

I chose to place the chips in a different order to ensure I knew what I was doing and not just copying the last question.


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