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I'm designing a system with a master board and a variable number of identical daughter boards that I would like to connect in a chain. The master board contains a microcontroller but the daughter boards don't contain anything intelligent. The master board will only connect to one daughter board, and each daughter board will be able to connect to a next daughter board.

I'd like to figure out a way for the master board to be able to detect how many boards are connected to it, and be able to send signals to each board depending on where that board is in the chain.

Does anyone have a good idea for this? The simpler the better.

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  • \$\begingroup\$ What is the nature of the "signals" that the master board wants to send to the daughter boards? \$\endgroup\$ – Dave Tweed Sep 17 '12 at 18:58
  • \$\begingroup\$ Dave, as long as I can enable or disable to correct chip select signal on a specific daughter board I'll be happy. \$\endgroup\$ – Marlon Smith Sep 17 '12 at 19:15
  • \$\begingroup\$ How many wires can we use to do it? Is there an upper limit on the number of daughter boards? \$\endgroup\$ – Dave Tweed Sep 17 '12 at 19:22
  • \$\begingroup\$ It's trivial if you put some intelligence in each daughter board. Something like a the 6-pin microcontrollers from Microchip or AVR costs less than $0.50 each and take up very little space. \$\endgroup\$ – Jim Paris Sep 17 '12 at 19:27
  • \$\begingroup\$ Dave, an upper limit would be around 16. \$\endgroup\$ – Marlon Smith Sep 17 '12 at 20:34
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The simplest way to create a generic "board select" signal is to create a distributed shift register, as shown below. This is similar to what you do when you use a 74xx595 as an I/O expander, and also similar to how JTAG works.

board select block diagram

The microcontroller can select any one (or even more than one) daughter board by shifting the appropriate pattern of ones and zeros into the flip-flops.

Each daughtercard also has an open-collector transistor that pulls down on an ACK line whenever it is selected. This allows the microcontroller to count how many daughtercards are present, by shifting a single one into the first card, and then counting how many clocks it takes for the ACK line to go high.

Note that the ACK line may not be necessary if you have some other means of determining that a board is selected, such as seeing whether it responds to a SPI bus cycle.

Note also that if you need an active-low board select signal, just use the not-Q output of the flip-flop.

This scheme does not need any sort of loopback on the last daughtercard.

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  • \$\begingroup\$ Using an open-collector output makes it possible to avoid requiring a loopback on the last card, but means that in at least some situations one will be trying to drive against a passive pull-up, increasing power consumption. If one is using connectors which have a switch which opens when a plug is inserted, using such a switch can provide a loopback facility without increasing power consumption. Alternatively, it's possible to use a resistor for the loopback connection; if another board is present, it will drive more powerfully than the resistor. Otherwise the resistor will "win". \$\endgroup\$ – supercat Sep 17 '12 at 21:39
  • \$\begingroup\$ @supercat: I'm not sure what your point is. Assuming a 5V supply, the ACK circuit draws less than 1mA when one board is selected, and nothing at all when no boards are selected. And like I said, it may not be necessary at all. \$\endgroup\$ – Dave Tweed Sep 17 '12 at 21:46
  • \$\begingroup\$ Whether or not the static current drawn by a pull-up on an open-collector bus will be significant depends upon the application. I like to try to design things to minimize static current consumption when practical; it's good to be aware of design techniques which can eliminate static current draw, though it's not necessary to use them in every case. The design requirements for different applications will sometimes favor different design techniques. \$\endgroup\$ – supercat Sep 17 '12 at 22:14
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If the daughter boards are just supposed to output signals received from the master, a common approach is to cascade 74HC595 or 74HC4094 shift register chips; each board has "register latch", "shift clock", and "data" inputs which are fed to the first shift register, and passes on the "register latch" and "shift clock" signals, along with the data output from the last shift register, to the next board. If one needs inputs as well as outputs, one can have each board also accept a "return data" input from the downstream board which feeds into zero or more 74HC165 shift registers, and have the output from the last register feed the "return data" input of the next upstream board. The last board in the chain should have its "data output" which would feed a non-existent next board to the "return input" which would come from that board.

In this way, the master device can determine how many shift registers there are by outputting a number of "0" bits which is known to be greater than the number of shift-register bits, confirming that the data return input is low, and then clocking out "1" bits until a "1" bit comes back on the data return.

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  • \$\begingroup\$ Thanks supercat, that's close to what I need. In my case, data is transmitted via SPI, but I could still use something like this just for the addressing. \$\endgroup\$ – Marlon Smith Sep 17 '12 at 21:04
  • \$\begingroup\$ @MarlonSmith: How many wires do you want to use for your connection? You could get things down to two outgoing and one return wire, though a design using three outgoing would require less circuitry and be easier to work with, and using four would require even less than that (four outgoing would essentially be Dave Tweed's circuit). \$\endgroup\$ – supercat Sep 17 '12 at 21:58
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If you use a SPI bus, you can simply daisy-chain your slaves that way: source: Wikipedia

The constraints are the following:

  • burst read and write are not possible
  • the slaves must all have the same SPI data size X
  • the master can determine exactly how many slaves are connected by lowering SS, sending a '1' on MOSI and watch it come back after Y clock cycles on SCLK: there are Y/X slaves connected.
  • if you need to read date from slaves (meaning the slaves have to inject their data in the stream of SPI data somehow) the protocol cannot be the usual SPI protocol (stateless slave, data read in one SPI transaction) because each slave has no way to know how many other slaves are connected, thus how many bit it must pass through unchanged, and where are the bits it can modify.
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  • \$\begingroup\$ Have you ever actually tried this in a real project? And since when does the "usual SPI protocol" involve a "stateless slave"? I can't think of a single SPI device I've worked with for which this would work. They all have internal registers, and attach special significance (e.g., register address) to the bits immediately following the slave select. \$\endgroup\$ – Dave Tweed Sep 22 '12 at 15:55

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