I have schematic for decoupling capacitors (3 set of 0.1uF,1nF,10pF): enter image description here And I've implemented that in this way: enter image description here And there is ADI reference for easy evaluation: enter image description here And the ground pins of decoupling caps will all connected to ground by polygone containing all pins in top and bottom. Also we have two stranger, 12GHz differential pair + clock trace. Is it acceptable? Do not tell anything and listen to the notes please.


The board have 4 layer 1.RF 2.GND(unbroken) 3.AVDD(unbroken) 4.signal

And as you can (have to!) see I have connected 3 AVDD pins of IC, together (by polygon), but the 3 AGND's are exactly in left side of the differential 12GHz pair. Unfortunately I will connect the top capacitors to two pin in left-side of C1's GND, because they are GND but are Digital GND (datasheet called them DGND and SDGND).I have idea it will be nice if I can place a bigger size (like 1204) of one of capacitors to bridge the right and left of differential pair, is it good idea (I prefer 1nF)?


The questions are:

|.Is it acceptable decoupling, rate it and if is poor give alternate idea

||.Is it good idea to bridge two side of differential pair? (because I think the bypasses must be between same GND & VDD but in this case they are not in good placement)

  • \$\begingroup\$ You do not have controlled impedances for 12 GHz traces You are making obvious errors and asking the wrong question. with mm wavelengths \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 6 '19 at 12:25
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    \$\begingroup\$ @TonyEErocketscientist I have calculated the impedance of 12 GHz differential traces by "Kicad" 's calculator and I think they are not important in this question since I want to ask another question exclusively for this differential trace, and please help me to improve my question. \$\endgroup\$ – mohammadsdtmnd Jan 6 '19 at 12:32
  • \$\begingroup\$ What chip is this and what current spectrum noise is generated here and elsewhere? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 6 '19 at 12:41
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    \$\begingroup\$ You're going to need thermal reliefs on all of the component pads connected to the AVDD polygon. Otherwise you'll get tombstoning when the board is manufactured, since the polygon will suck away all the heat and won't reflow properly. \$\endgroup\$ – DerStrom8 Jan 6 '19 at 13:06
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    \$\begingroup\$ Tombstoning is caused by all these things: trace/board design, pad design, component and board oxidation, solder paste, stencil design, print process, placement process, and reflow process. NOT just ONE thing \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 6 '19 at 13:51

Firstly look at the eval board gerbers and copy them, not always perfect but usually a reasonable guide to how to decouple such things.

Secondly those packages look huge, (0805? 0603? something like that), for at least the smallest values you really want 0402 or even 0201 to get the package parasitic inductance down low enough.

How you ground the caps is REALLY going to matter, think LOTS of stitching vias.

Were I doing a from scratch design I might bury the RF feedback lines on layer 3 done as stripline with a local ground pour on L4 and L2 (And LOTS of stitching), so I could put the caps on L1 right above the rf lines, but it makes board stackup very important so you would not be able to use the cheap PCB pooling services.

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  • \$\begingroup\$ Grateful to your inspiring idea, also can you give me your idea about 2 questions I've asked in "Finally"? \$\endgroup\$ – mohammadsdtmnd Jan 6 '19 at 15:48

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