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Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation board.
First I had simply the VHDL file, did the pin assignement, and it worked fine in simulation and on the real board.

Then I tried to create a "BDF" and replace the clk signal by the output of a PLL block.
With this approach, Quartus keeps warning me that the PLL block is "synthesized away" and that there are "No clocks defined in design".

I read some tutorial on integrating such a PLL block from the IP catalog, but I can't find what's wrong with my setup.
Any advice?

This is how my BDF looks like: enter image description here

Here the code of spi_slave:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity spi_slave is
  port (
    RESET_in    : in  std_logic;
    CLK_in      : in  std_logic;
    SPI_CLK     : in std_logic;
    SPI_SS      : in std_logic;
    SPI_MOSI    : in  std_logic;
    SPI_MISO    : out std_logic;
    SPI_DONE    : out std_logic;
    DataToTx    : in std_logic_vector(7 downto 0);
    DataToTxLoad: in std_logic;
    DataRxd     : out std_logic_vector(7 downto 0)
    );
end spi_slave;

architecture Behavioral of spi_slave is

    signal SCLK_latched, SCLK_old : std_logic;
    signal SS_latched, SS_old : std_logic;
    signal MOSI_latched: std_logic;
    signal TxData : std_logic_vector(7 downto 0);
    signal index: natural range 0 to 7;
    signal RxdData : std_logic_vector(7 downto 0);
     signal comparison_value : integer;
begin

 --
 -- Sync process
 --

process(CLK_in, RESET_in)

    begin
        if (RESET_in = '1') then
            RxdData <= "00000000";
            index <= 7;
            TxData <= "00000000";
            SCLK_old <= '0';
            SCLK_latched <= '0';
            SS_old <= '0';
            SS_latched <= '0';
            SPI_DONE <= '0';
            MOSI_latched <= '0';
        elsif( rising_edge(CLK_in) ) then
            SCLK_latched <= SPI_CLK;
            SCLK_old <= SCLK_latched;
            SS_latched <= SPI_SS;
            SS_old <= SS_latched;
            -- SPI_done <= '0';
            MOSI_latched <= SPI_MOSI;

            if(DataToTxLoad = '1') then
                TxData <= DataToTx;
            end if;

            if (SS_old = '1' and SS_latched = '0') then
                index <= 7;
            end if;

            if( SS_latched = '0' ) then
                if(SCLK_old = '0' and SCLK_latched = '1') then
                    RxdData <= RxdData(6 downto 0) & MOSI_latched;
                    if(index = 0) then -- cycle ended
                        index <= 7;
                    else
                        index <= index-1;
                    end if;
                elsif(SCLK_old = '1' and SCLK_latched = '0') then
                    if( index = 7 ) then
                        if (to_integer(unsigned(RxdData)) = 160) then
                            SPI_DONE <= '1';
                        end if;
                    end if;
                    TxData <= TxData(6 downto 0) & '1';
                end if;
            end if;
        end if;
end process;

   --
   -- Combinational assignments
   --

   SPI_MISO <= TxData(7);
   DataRxd <= RxdData;

end Behavioral;

PIN_N5 is a clock input, and everything works fine without the pll block and N5 directly connected to CLK_in.

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  • \$\begingroup\$ That makes me think the spi logic was synthesized away as well and therefore there was nothing to be clocked by the PLL so it was removed. Maybe try defining a pin assignment for the reset? Seems like it should be fine without it though... \$\endgroup\$ – ks0ze Jan 6 at 16:29
  • \$\begingroup\$ @ks0ze: Seems you are right; connecting this pin solves the problem. And I believe meanwhile I understand the reason: The "if (RESET_in = '1') " with a default level of "1" for RESET_in makes CLK_in no longer relevant. Correct? \$\endgroup\$ – mic Jan 6 at 17:16
  • \$\begingroup\$ I'm not sure how Intel/Altera treats uninitialized signal since I mostly deal with Xilinx FPGAs, but essentially that's what I'm assuming happened \$\endgroup\$ – ks0ze Jan 6 at 17:37

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