I'm working on a project where I have to do some unidirectional logic level shifting. I'm not able to get any chip to do it at this moment (it's late at night) so I looked up some DIY solutions and came across this design(Method 1) i.e. a potential divider. The warning associated with it confuses me however.
This method works for slow signals, but it’s not very reliable.
My question is why won't it work for slow signals? It's just a voltage divider so there's no lead/lag components or setup and hold times for logic gates. If anything it should better with slow signals, but why not?