SPI using STM32's DMA sends one word too much

Question

On an STM32F103 I configure SPI in 16bit wide mode and set up a DMA transfer to transmit one byte:

SPI2->CR1 &= ~SPI_CR1_SPE;
SPI2->CR2 = 0;
SPI2->CR1 =
    SPI_CR1_SSM |
    SPI_CR1_SSI |
    SPI_CR1_DFF |
    SPI_CR1_SPE |
    /* Some baud rate flags */ |
    SPI_CR1_MSTR;

/* Set up DMA transfers */
DMA1_Channel4->CMAR = (uint32_t) /* some buffer */;
DMA1_Channel4->CPAR = (uint32_t) &SPI2->DR;
DMA1_Channel4->CNDTR = 1;
DMA1_Channel4->CCR = DMA_CCR4_MINC | DMA_CCR4_EN;

uint16_t dummy = 0xFFFF;
DMA1_Channel5->CMAR = (uint32_t) &dummy;
DMA1_Channel5->CPAR = (uint32_t) &SPI2->DR;
DMA1_Channel5->CNDTR = 1;
DMA1_Channel5->CCR = DMA_CCR5_DIR | DMA_CCR5_EN;

/* Transfer */
SPI2->CR1 |= SPI_CR1_SPE;
DMA1->IFCR = DMA_IFCR_CTCIF5 | DMA_IFCR_CTCIF4;
SPI2->CR2 |= SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN;
SPI2->CR1 |= SPI_CR1_SPE;

I connected a counter to the SPI's clock line and the above code produces 32 clocks. No interrupts are enabled or whatsoever; the behaviour can constantly be observed. If the DMA is set up to transmit zero bytes, no clocks are generated.

Why does it clock out 32 bits?

Answer 1

Discovered the issue: The SPI's CRC unit has been enabled by accident, so the excess transfer stems from the CRC checksum. This was impossible to deduct from the above source; enabling CRC happened somewhere else and I missed it.

Answer 2

It's because the code tells the SPI to receive one word via DMA channel 4 and transmit one word via DMA channel 5 and then both channels are enabled simultaneously. Most likely enabling the DMA reception already triggers a transfer as well. Try enabling only one of TXDMAEN or RXDMAEN bits.