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I was considering designing an SRAM memory array. For my design to be useful in a certain system, I need to have several cells in a row (e.g. 1024, 2048). In textbooks I have seen examples of arrays with typically 8-cell words (1 byte per word). Is it possible to have as many as 1024 cells (128 bytes) in an SRAM word?

One problem that comes to mind immediately is that driving such a long word-line may require big drivers. But this would be design problem, not a fundamental one.

Could there be any other issue?

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    \$\begingroup\$ This question seems effectively pointless - how were you planning to implement this? If you mean practical custom silicon you'll need a huge budget and to do a lot of research no matter what you do, and if you don't mean custom silicon you're just going to be buildings something that meets your needs but is structurally different - ie, multiple available chips in parallel or a partially automated mapping of FPGA internal resources. \$\endgroup\$ – Chris Stratton Jan 9 at 20:12
  • \$\begingroup\$ As a student I have to regard everything as implementable - at first. \$\endgroup\$ – adi2293 Jan 9 at 22:01
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You also have to worry about driving long bit lines that run orthogonally to the word lines, and the delay of a long wire is proportional to the square of the length.

Therefore, memory arrays are typically designed to be more or less square so that neither the word lines nor the bit lines cause unacceptable delay. The number of bits in a row may be much more than the number of bits in the output word, and the actual desired bits are then demultiplexed from the wide row.

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  • \$\begingroup\$ Thanks! The square argument kind of makes sense. But how come say, Cypress, sells a chip of organization 16M by 72 bits? Could you provide a reference that talks about these things. Things like these are rarely talked of in classrooms! \$\endgroup\$ – adi2293 Jan 10 at 2:53
  • \$\begingroup\$ It looks like the cypress part uses either 18 or 36 bits internally and then joins them together. cypress.com/file/45151/download \$\endgroup\$ – pjc50 Jan 10 at 14:13
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72 bit wide would be used for a system with 64 bit memory and 8 bits of Error Detection And Correction (EDAC) as one example. https://4donline.ihs.com/images/VipMasterIC/IC/IDTI/IDTIS02246/IDTIS02246-1.pdf?hkey=EF798316E3902B6ED9A73243A3159BB0

I used this once in a memory subsystem. The controller handled 8, 16, 32 ,and 64 bit transfers between the multiple system processors and up to 8 memory cards arranged as 72 bits by a large number of addresses. A processor on the controller wrote to all memory on startup thru the EDAC to ensure good data at all locations so that an 8-16-32 bit write would result in a 64-bit read, stuffing in the 8-16-32 bits of new data, and then a 64-bit write back into the array.

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