Hi) I want to calculate the width of my 100Mb Fast Ethernet MDI diff pairs. I've got some software (TXLINE 2003 Microstrip). I have 4 layers. The second layer is GND, the third is power, top and bottom are signal layers. I have one diff pair on the top and one on the bottom. For the top everything is clear, I took the height parameter as distance between top layer and GND. But what should I do for the bottom layer? What layer should I choose to calculate the distance (Power layer or GND)? I have also heard that if one chooses Power layer as reference layer for calculation of width then one need to place 10nF capacitors between power and GND on boths sides of MDI diffpairs. Is this correct?


1 Answer 1


If your routing a diff pair you need a ground plane underneath it that is continuous, as the capacitance between the traces and ground needs to be controlled to some degree. One of the best ways to do this is to have the top layer be signal and the second layer be ground. (There are more than one ways to have an impedance controlled trace, for simplicity I'll describe only one)

The idea behind a microstrip is that the current flows on the signal, and the return current flows back on the ground plane below, this keeps impedance low and lets it function like a transmission line, an you can minimize bad things like reflections and attenuation that would reduce the signal that the trace carries.

Don't use a power plane for the basis of a microstrip, this interferes with return current (needs to be through ground) and will result in undesirable characteristics of your transmission line.

While it is possible to to build a microstrip transmission line with a power plane, this is a bad practice. Why? because if you do use the power plane you'll need stitching caps, and each cap will have on the order of 10nH of parasitic inductance, this will inhibit the return current. If your ok with increasing the inductance and lowering the rise time then go for it.

enter image description here


If your routing PCIE keep the diff pairs on the top layer with ground underneath, here is a guide:

PCIE Express Routing

  • \$\begingroup\$ Thank you for the respone!) The matter is that I am using PCI Express x1 connector. And it has one diff pair on the A side and one on the B side, so I think that I'm bound to spread diff pairs on two layers. What is the perpose of the stiching cups and how should I use them, should I connect ground plane to the power plane using caps along the signal line or just near IC output? And also what is the distance I should use to calculate the trace width to match impedance? Should I use the distance to ground or to power plane in the case if the signal is referenced to power plane? \$\endgroup\$
    – Andy
    Jan 11, 2019 at 7:36
  • \$\begingroup\$ meta.stackexchange.com/questions/126180/… \$\endgroup\$
    – Voltage Spike
    Jan 11, 2019 at 22:11

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.