For a school project , I'm trying to design an 8-bit standard ALU in VHDL, With a twist. I want it to take the input in serial form but show the output in the parallel form. here is a code of mine :

library IEEE;
use ieee.NUMERIC_STD.all;
---------- ALU 8-bit VHDL ---------------------
entity ALU is
  generic ( 
     constant N: natural := 1  -- number of shited or rotated bits

    Port (
    A, B     : in  STD_LOGIC_VECTOR(7 downto 0);  -- 2 inputs 8-bit
    ALU_Sel  : in  STD_LOGIC_VECTOR(3 downto 0);  -- 1 input 4-bit for 
selecting function
    ALU_Out   : out  STD_LOGIC_VECTOR(7 downto 0); -- 1 output 8-bit 
    Carryout : out std_logic        -- Carryout flag
end ALU; 
architecture Behavioral of ALU is

signal ALU_Result : std_logic_vector (7 downto 0);
signal tmp: std_logic_vector (8 downto 0);

  case(ALU_Sel) is
  when "0000" => -- Addition
   ALU_Result <= A + B ; 
  when "0001" => -- Subtraction
   ALU_Result <= A - B ;
  when "0010" => -- Multiplication
   ALU_Result <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) * 
to_integer(unsigned(B))),8)) ;
  when "0011" => -- Division
   ALU_Result <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 
to_integer(unsigned(B)),8)) ;
  when "0100" => -- Logical shift left
   ALU_Result <= std_logic_vector(unsigned(A) sll N);
  when "0101" => -- Logical shift right
   ALU_Result <= std_logic_vector(unsigned(A) srl N);
  when "0110" => --  Rotate left
   ALU_Result <= std_logic_vector(unsigned(A) rol N);
  when "0111" => -- Rotate right
   ALU_Result <= std_logic_vector(unsigned(A) ror N);
  when "1000" => -- Logical and 
   ALU_Result <= A and B;
  when "1001" => -- Logical or
   ALU_Result <= A or B;
  when "1010" => -- Logical xor 
   ALU_Result <= A xor B;
  when "1011" => -- Logical nor
   ALU_Result <= A nor B;
  when "1100" => -- Logical nand 
   ALU_Result <= A nand B;
  when "1101" => -- Logical xnor
   ALU_Result <= A xnor B;
  when "1110" => -- Greater comparison
   if(A>B) then
     ALU_Result <= x"01" ;
    ALU_Result <= x"00" ;
   end if; 
  when "1111" => -- Equal comparison   
   if(A=B) then
    ALU_Result <= x"01" ;
    ALU_Result <= x"00" ;
   end if;
  when others => ALU_Result <= A + B ; 
  end case;
 end process;
 ALU_Out <= ALU_Result; -- ALU out
 tmp <= ('0' & A) + ('0' & B);
 Carryout <= tmp(8); -- Carryout flag
end Behavioral; 

this code is parallel in parallel out. also I have the code for an SIPO to attach to the input of the ALU code in order to have it take serial input :

library IEEE;

entity SerinParout is

CLKs : in std_logic;
CLKp : out std_logic;
RST  : in std_logic;
Serial1: in std_logic;

Parallel1 : out std_logic_vector(7 downto 0));

end SerinParout;

architecture Behavioral of SerinParout is
signal temp : std_logic_vector(6 downto 0);
signal counter: integer;
  if RST='1' then
  CLKp <='0';

     if(CLKs='1' and CLKs'event) then
       if (counter<7) then
           CLKp <='0';
       end if;
     end if;

 end if; 
 end process;
end Behavioral;

my question is syntax wise what do I specifically change in the former code to have it feed of the latter therefore forming an ALU that is attached to a SIPO in the input forming an ALU that takes input in a serial form. thank you for your attention.

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closed as too broad by Eugene Sh., Dave Tweed Jan 10 at 22:28

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • 3
    \$\begingroup\$ Take a regular ALU and connect to to a SIPO register on the input. \$\endgroup\$ – Eugene Sh. Jan 10 at 22:23
  • 3
    \$\begingroup\$ Or write a 1-bit ALU and stick a SIPO register on the output. \$\endgroup\$ – Wouter van Ooijen Jan 10 at 22:32
  • \$\begingroup\$ This is either a silly idea, or there's a big part you are leaving out. Realize that the majority of the time, at least one input of the ALU is a previous output, often quite recently so. So this would make no sense unless you were pairing the ALU with a register file or storage that had the same arrangement in reverse. \$\endgroup\$ – Chris Stratton Jan 10 at 22:54
  • 1
    \$\begingroup\$ do you realize that you are asking how to design a serial to parallel converter? \$\endgroup\$ – jsotola Jan 10 at 23:31
  • 1
    \$\begingroup\$ Your edit does not fix the problems with your question. EESE is not a code writing service. You need to make an actual attempt at the serial-parallel conversion yourself. This is obviously homework (as it's a nonsense task for any real project), and an inability to do that suggests you did not pay attention in previous class segments, so you'll need to review the previous class material. \$\endgroup\$ – Chris Stratton Jan 11 at 17:24

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