Verilog - Using 'define' to declare a constant created by a 'parameter'

Question

Pardon the wordiness of the question's title. How would you accomplish the following. I have this parameter:

parameter BUS_SIZE = 16;

And I want to use it later in the code to declare some constants. Currently, I am doing this:

someReg <= 16'h8F;

The hardcoded 16'h8F means that the code is not flexible, and defeats the purpose of the parameter.

What is the proper way to declare this constant? This is what I've come up with, but I'm not sure it would work or if there is something more elegant available:

`define dBUS_SIZE BUS_SIZE
...
someReg <= `dBUS_SIZE'h8F;

Answer 1

There's usually no need to do this in Verilog. (You must be coming from VHDL) Numeric literals get implicitly padded with 0's or truncated to fit into the assignment LHS variable. This also happens when used in most expressions.

someReg <= 'h8f;

There are a few exceptions that require the exact size, like in the middle of a concatenation. For that you can use a bitwise OR.

biggerReg <= {prefixReg, {BUS_SIZE{1'b0}}|8'h8f, suffixReg};

SystemVerilog has a bit-sizing cast that makes this a little simpler

biggerReg <= {prefixReg, BUS_SIZE'('h8f}, suffixReg};