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I am using the Altera Quartus II PinPlanner to enter all my pin details for my FPGA design. Some of the pins are connected to the SPI configuration bus of this ADC.

As can be seen on page 8, the 3 pins SCLK, SDATA, and SEN must be driven at 3.3V. Now the pin planner gives me three different 3.3V options:

  • 3.3V LVCMOS
  • 3.3V LVTTL
  • 3.3V PCML

Which of these I/O standards should I use for my ADC?

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Whenever you see a VIH specification of 2.4 V and VIL of 0.8 V — i.e., fixed voltages, not a fraction of the supply voltage — that's LVTTL.

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