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In his book "Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog)" the author said : 'The optional output register can be used to obtain a fully pipelined implementation with better time and higher clock speed predictability ' .

Where the aforementioned output register is indicated in the diagram below :

enter image description here

Question : How does this additional register permit using higher clock speeds ?

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That statement is too simple.

Following that statement any design can be sped up to run at Terra-herz just be adding more and more registers. But we know that is not the case.

In general if a logic cone (A group of gates with inputs and an output) stage takes X nano-seconds, you can sometimes split the logic in two parts each taking X/2 nano-seconds by adding a register stage in the middle. But you do not get exactly X/2 because adding the register comes with it's own timing cost.

To begin with: you have to subtract the set-up and hold time of the register from the time you gain. On top of that you have something called 'clock uncertainty' which you have to subtract. Then you have the delay of the register: clock to out.

But adding a register stage also upsets all the timing in any feedback path. refer to the diagram above:
If L1 is too slow and you add a register stage, the path from R1 back into R1 suddenly takes an extra clock cycle and the resulting circuit will no longer behave the same. That is why e.g. in a CPU you suddenly have to implement 'register folding' and other techniques to cope with a long pipeline.

Conclusion:
Yes, you can sometimes speed up a design by adding register stages but it is no panacea, it requires thought and often you have to re-think your design: back to the drawing board.

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L1 and L2 are effectively live. For other than propagation delay whenever the input changes the output changes immediately. R1 and R2 are clocked registers. Their state only changes on a clock edge.

Suppose a timing requirement needs to be met for the output. Let's say 1 second. That the output has to hold for 1 second so that whatever this is connected to gets a good input. Also, let's say that the processing time was also 1 second. It would take 2 seconds to update the output. One to hold the output and one to process. This is because the output of L2 is live and would be unstable during the processing time. Therefore the output cannot be trusted during processing.

If R2 is added it would only take 1 second to update the output. This is because R2 could hold the output while the processing occurred. Because R2 will hold the output regardless of what L2 does during processing. Once L2 is stable it gets clocked into R2 and the next processing cycle can begin immediately.

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