Today after class we were left with an exercise of creating schematics and combining two components we learned about today. The exercise is to combine two 1kx3 NOR MOS PROM components into a 2kx6 PROM component with floating gate transistor programming. (1k ones also use this).
I wanted to check if my understanding is correct so i'm posting this to get replies on whether something doesn't look right or if something is missing. I am just suppose to draw a memory cell of these ROMs and not the entire logic behind it so sense amps and other write/read buffers are omitted.
I have drawn a decoder which decodes 10 adress lines into 1024 word lines and i have 3 bitlines connected to a pull-up network consisted of p-mos transistors. The interconnections in the memory cell are programmed by floating gate transistors. I have drawn with 3 lines in the base to indicate that.
Is this how NOR type is supposed to be connected? I'm sort of mixing the NOR and NAND types and am not sure if this is correct. If this is correct how would i make a NAND type since all that's different probably is the configuration of the interconnection transistors.