0
\$\begingroup\$

enter image description here

These are some lecture notes for my module, im pretty sure its wrong. Shouldn't the Q point be at Vcc/2? Not Vce(sat)+Vcc / 2?

Even if it were to be half way between Vce(sat) and Vcc It would be Vcc-Vce(sat) / 2 + Vce(sat)

But the diagram doesn't look like Q is centred between Vcc and Vce(sat)

\$\endgroup\$
1
\$\begingroup\$

Based on the drawing, the optimum Q point is the middle between Vcesat and Vcc, Hence, we have

Vce=Vcesat + (Vcc-Vcesat)/2=(Vcc+Vcesat)/2

\$\endgroup\$
  • \$\begingroup\$ Optimum for what? Small signal or large? 0.1% THD or 10%? \$\endgroup\$ – Sunnyskyguy EE75 Jan 12 at 17:52
  • \$\begingroup\$ OK - I agree to your comment, of course. "Optimum" is a word that should be avoided in electronics because each design is always a trade-off between several confllcting requirements. My comment was nothing else than an answer to the question of "maximising the peak-to-peak voltage). However, even this maximum is questionable...... In summary, you are right, I should not use the term "optimum". \$\endgroup\$ – LvW Jan 13 at 11:06
  • \$\begingroup\$ yes the large signal model must use a different Q point than this. \$\endgroup\$ – Sunnyskyguy EE75 Jan 13 at 15:54
1
\$\begingroup\$

Q point= \$V_C=\dfrac{Vcc+V_{CE(sat@Ic)}}{2}\$ is mathematically correct ,if you ignore the quality of the "swing"

The current hFE drops to 10% of its max value near Vce_sat but since all transistor have a wide variation, they standardize Vce(sat)test with Ic:Ib=10:1 (except special parts with hFE>400), 20:1 to 50:1.

Details

What THD do you need from non-linearity near Vce(sat)?

The Vce(sat) curve is a combination of the Vce(sat) at low current e.g. 0.05~0.2V and the bulk series resistance, Rce which can be defined by the slope of the curve ΔVce/ΔIce and then the knee to a constant hFE. Depending on the ratio of Imax used , this can exceed Vce=2V. Unless you have a curve-tracer to test every part is give some margin such as always Vce>2V or Vce>2Vce(sat)@Imax with Idc+Iac full swing sine..

So my Rule of thumb is \$V_C=\dfrac{Vcc+2V}{2}\$ or \$V_C=\dfrac{Vcc+2V_{ce(sat)}}{2}\$ whichever is greater.enter image description here

If you measure a maximum swing sinewave and measure the THD or difference between Vp- and p+ compared to the average, you will see when Vp- shrinks due to hFE reduction.

Also never vary the collector current more than 2 decades and expect a textbook sinewave when the gain depends on hFE variation as much as it does with current. This can be seen on datasheets with hFE vs I vs Vce.

Yes the graph is misleading and is a good example of a non-optimal or non-symmetrical point.

enter image description here

Vce(sat)=0.6Vmax @ 100mA is also misleading for linear operation as this applies to a switch operation. enter image description here

\$\endgroup\$
  • \$\begingroup\$ @ Sunny excellent writing and figures, sir. \$\endgroup\$ – analogsystemsrf Jan 12 at 18:37
  • \$\begingroup\$ Of course in all this myopic discussion we are assuming Re=0 and thus Ve=0 which would be added to the equation if not 0. This is why the Large signal model applies here which includes Rce effiectively \$\endgroup\$ – Sunnyskyguy EE75 Jan 12 at 18:42
  • \$\begingroup\$ so effectively Re ought to be > Rce for linear operation which is done in complementary push-pull amps then negative feedback to improve it. \$\endgroup\$ – Sunnyskyguy EE75 Jan 12 at 18:49

Your Answer

By clicking "Post Your Answer", you agree to our terms of service, privacy policy and cookie policy