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I have a question to someone who is familiar with PSpice analysis. I have a simple circuit as below and everything works good with "typical" simulation - dstm1 gives positive impulses continously and couter 74393 count till output A and C have high signal, then via AND and OR gate signal reset 74393 counter. When I change simulation to "worst case" I have situation when output C has high signal and in the meantime it is rising signal on output A and clr (counter reset). Is it possible to make some delay on AND gate? Or is it other way to fix worst case simulation to make it works properly? Thank you in advance for any advices. CIRCUIT Typical: TYPICAL Worst case: WORST CASE Worst case with lower frequency: worst case2

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  • \$\begingroup\$ It looks like your clock frequency is too high for operation under worst-case conditions. What makes you think that the simulation results are incorrect? Can you point to a specific delay in your simulation that exceeds the datasheet maximum value? \$\endgroup\$ – Elliot Alderson Jan 12 at 20:12
  • \$\begingroup\$ Thank you for your answer. I have edited my post and added worst case simulation with lower frequency of clock - no positive results. The point of this exercise is to find out how to modify given circuit to make it works also with worst case simulation. I'm not sure but in my opinion it seems that maybe there is some delay needed on AND gate but I'm not sure whether we are able to create it. \$\endgroup\$ – Grzegorz Jan 12 at 21:11
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You have combinational feedback, from the outputs of the 393 through the AND gate and OR gate back to the CLR input of the 393. This is an inherently dangerous design style. Adding delay at the AND gate is not a good fix.

I'm not sure what it is you are trying to make this circuit do, but you might need to replace the OR gate with another AND gate so the the counter is only reset when clr_1 is also high. Then make sure that the delay between the falling clock edge and the assertion of clr_1 is long enough to allow the counter outputs and the first AND gate to reach their final values.

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  • \$\begingroup\$ Second AND gate could be the good solution but counter need CLR signal at startup to start counting output signals - how to do that? To be honest - the point is to make this circuit works using typical and also worst case timing model. 74393 has to count till high signal will be at output A and C and then counter should reset and make another the same circuit. I can modify circuit components, values of parameters of all components and so on. It is an excercise from my studies. \$\endgroup\$ – Grzegorz Jan 14 at 22:23

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