I have a question to someone who is familiar with PSpice analysis. I have a simple circuit as below and everything works good with "typical" simulation - dstm1 gives positive impulses continously and couter 74393 count till output A and C have high signal, then via AND and OR gate signal reset 74393 counter. When I change simulation to "worst case" I have situation when output C has high signal and in the meantime it is rising signal on output A and clr (counter reset). Is it possible to make some delay on AND gate? Or is it other way to fix worst case simulation to make it works properly? Thank you in advance for any advices. Typical: Worst case: Worst case with lower frequency:
You have combinational feedback, from the outputs of the 393 through the AND gate and OR gate back to the CLR input of the 393. This is an inherently dangerous design style. Adding delay at the AND gate is not a good fix.
I'm not sure what it is you are trying to make this circuit do, but you might need to replace the OR gate with another AND gate so the the counter is only reset when clr_1 is also high. Then make sure that the delay between the falling clock edge and the assertion of clr_1 is long enough to allow the counter outputs and the first AND gate to reach their final values.