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As in the title: what exactly is the impact of input bias current in Sallen-Key topology, for example the one below:

enter image description here

I read that it can matter significantly, however I did not find anything more on this matter.

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  • \$\begingroup\$ Bias current does not affect the small-signal behavior of an opamp. \$\endgroup\$ – analogsystemsrf Jan 13 at 3:09
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Where did you read that it "can matter significantly"? Well - in principle, it can matter, but only in case you have selected a very bad design strategy with very large resistances and very small capacitors. I assume - in spite of the fact that you spoke about "bias" currents only - that your question concerns the finite input impedance of opamps in general, right?

Of course, each real opamp has a finite input impedance and - besides a DC bias current - there will be always a small ac current into the opamp input terminals. With other words: The opamp constitutes a load to the passive network and - thus - influences the desired filter proprties. (And the same applies to the finite output impedance of the opamp).

However, if you follow the general rules for opamp applications - not to use extremely large resistor values resp. small capacitor values - neither the input nor the output impedances of the opamp play a measureable role for the filter properties. In this context, it is important to realize that there are other non-idealities which have much more influence (availabilty of the calculated ideal values, parts tolerances, frequency-dependent gain of theopamp,parasitics at the nodes,...).

If possible, resistor values below app. 100kohms and capacitor values above 20 pF should be used.

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  • \$\begingroup\$ I guess I misunderstood the article. It says "But more critical, high input bias currents in the nano or micro ampere range may motivate you to lower your resistors in your circuit. When you do this, you will increase the capacitors in order to meet your filter cutoff frequency requirements.". Thank you anyway:) \$\endgroup\$ – Em Ka Jan 13 at 12:25
  • \$\begingroup\$ Yes - that is one of the trade-offs I have mentioned: To find the "best" combination of resistors and capacitors for realizing a certain time constant. \$\endgroup\$ – LvW Jan 13 at 12:41
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The bias current is a DC characteristic and will not affect the AC characteristics.

In your schematic, assuming Vin is low impedance, it will cause an output offset of -Ib*(R1+R2).

There may be some input resistance or capacitance that could have an effect on the cutoff etc., but Ib is modeled as an ideal current source, which has infinite impedance.

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