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I am entering the pin information of my FPGA design using the Altera Quartus II PinPlanner. One of the components of my design is PCIe, and I am having troubles understanding the "I/O standard" associated with the PCIe data pins (one rx and tx for each PCIe lane).

This website claims that the PCIe lines are LVDS. However, looking at the example given for my FPGA devkit (which contains PCIe) I see that they are using either 1.5-V PCML or 2.5V I/O standards, not LVDS.

What is the I/O standard associated to the PCIe data line? Could the Altera Cyclone IV require a PCIe I/O standard that is somehow different from the PCIe electrical specifications?

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Did You try typing "PCI Express" in Google and give it a shot to feel lucky, huh? Wiki clearly says:

At the electrical level, each lane consists of two unidirectional LVDS or PCML pairs at 2.525 Gbit/s.

http://en.wikipedia.org/wiki/PCI_Express

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Refer to the transceiver architecture document for your device (e.g. for Cyclone IV it's http://www.altera.com/literature/hb/cyclone-iv/cyiv-52001.pdf). On this device, the refclk input supports a handful of standards but HCSL is recommended for PCIe, the transmitters only support 1.5V PCML and the receivers support LVDS, LVPECL and PCML at a few different voltages. In my particular design (using Cyclone IV) I used 1.5-V PCML for both the Rx and Tx lines and HCSL for refclk (I'm also using an HCSL clock driver on my board).

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