I am entering the pin information of my FPGA design using the Altera Quartus II PinPlanner. One of the components of my design is PCIe, and I am having troubles understanding the "I/O standard" associated with the PCIe data pins (one rx and tx for each PCIe lane).
This website claims that the PCIe lines are LVDS. However, looking at the example given for my FPGA devkit (which contains PCIe) I see that they are using either 1.5-V PCML or 2.5V I/O standards, not LVDS.
What is the I/O standard associated to the PCIe data line? Could the Altera Cyclone IV require a PCIe I/O standard that is somehow different from the PCIe electrical specifications?