# Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required effect of rst_nb and rst_na.

There are two options as far as I know to have synchronized rstsync_nb:

1) ANDed two reset and then sync'd

2) Both resets are sync'd , ANDed and again sync'd

General guideline is to use reset which is not output from combinatorial logic because it is glitch prone.

To have glitch free sync'zer scheme which option is better for combining multiple resets?

Any other mechanism?

Edit : Reset Synchronizer

Depending on what you mean by glitch, the lower schematic might make one due to unequal latency between the two synchronizers before the AND gate. Also, there is no clock shown for the following sync. I vote for the upper schematic for both its relative simplicity and no parallel unequal paths.

For Solution 1, you need this constraint, otherwise the ANDed result might be to short for you synchronizer and you'll never see a reset signal after your synchronizer circuit.

For solution 2, both stage 1 synchronizers will synchronize the result pulse, but the resulting reset of both synchronizers might be visible in different cycles, thus, the and-gate will not create a reset at it's output. The 2nd stage synchronizer is not needed, because both output are synchronous to the same clock domain.

Btw. an and-gate isn't the correct logic function to AND two low-active signals ...

So, if you can create such a constraint on your inputs, then it's good, otherwise you need a more complex synchronizer circuit, made up of basic synchronizers. One solution might be synchronizers which lock themselfs and clear when the other reset arrives.

So why is it so complex in your case?

• You use asynchronous resets, which shouldn't be used at all.
• You use low-active resets, which shouldn't be used at all.
• Usage of AND Gate : Since both are active low and ANDed, if any one of the reset becomes low the output of AND gate becomes low irrespective of level of other reset. So what is the problem having AND gate? I am using AND gate to take effect of both the reset. – Prakash Darji Jan 22 at 6:05
• I assume that, If system have async reset then we have to sync it on per clock. To have async assertion and sync deassertion to deal with recovery/removal issue. – Prakash Darji Jan 22 at 6:08
• The function you describe in your first comment is an OR. Then an AND gate is correct. Your original post reads (for me) that you want to apply the reset only if both resets are active. – Paebbels Jan 22 at 10:08
• No I want effect of both the reset. It is only possible with AND gate. – Prakash Darji Jan 23 at 3:08

Use schematic (1). Provided your 'reset synchroniser' is a suitable circuit, you'll get a clock-synchronous reset in each clock domain.

You don't state which technologies you're targeting your circuit for: ASIC, FPGA, CPLD, discrete logic etc.

For a suitable circuit in an FPGA with asynchronous presets (or push-back to resets) on flip-flops, I use a 4-stage shift register. The preset asynchronously loads the SR with all '1's. Otherwise the shift register is always shifting in '0's. The circuit needs no timing constraints on the reset input to DFFs relationship. The first DFF in the SR may go metastable when the preset is negated as its clock active edge arrives. That's fine as the next SR stage will resolve it to a stable logic level. The incoming reset signals will need to be glitch-free but that's not difficult to get from an external reset circuit. The result is an active-high internal reset with a duration of at least 4 clocks.

But pick the reset synchroniser suited to the technology you will use.

• I am targeting for ASIC technology. As you stated, "The incoming reset signals will need to be glitch-free but that's not difficult to get from an external reset circuit". Assume my both rst_na and rst_nb both are generated from combinational circuit then which option is better? – Prakash Darji Jan 22 at 6:00
• Edited Que with Reset Synchronizer Circuit. – Prakash Darji Jan 22 at 6:15