In addition to your solution, you need a reset pulsewidth constraint.
For Solution 1, you need this constraint, otherwise the ANDed result might be to short for you synchronizer and you'll never see a reset signal after your synchronizer circuit.
For solution 2, both stage 1 synchronizers will synchronize the result pulse, but the resulting reset of both synchronizers might be visible in different cycles, thus, the and-gate will not create a reset at it's output. The 2nd stage synchronizer is not needed, because both output are synchronous to the same clock domain.
Btw. an and-gate isn't the correct logic function to AND two low-active signals ...
So, if you can create such a constraint on your inputs, then it's good, otherwise you need a more complex synchronizer circuit, made up of basic synchronizers. One solution might be synchronizers which lock themselfs and clear when the other reset arrives.
So why is it so complex in your case?
- You use asynchronous resets, which shouldn't be used at all.
- You use low-active resets, which shouldn't be used at all.