H, I'm trying to understand the below code what how many FFs would be required when synthesis.
wire aclk; reg [2:0] a; reg [2:0] b; always @(posedge aclk) begin a <= b; b = a+1; end
wire aclk; reg [2:0] a; reg [2:0] b; always @(posedge aclk) begin b = a+1; a <= b; end
I'm confused that TEST1 and TEST2. I think 2 above codes are working as the same, But I've got the different result of synthesis.
First is 6FFs and last thing is 3FFs,
So I'm confusing this.