# How many flip-flips would this code require?

H, I'm trying to understand the below code what how many FFs would be required when synthesis.

TEST1.

wire aclk;
reg [2:0] a;
reg [2:0] b;

always @(posedge aclk)
begin

a <= b;
b = a+1;
end


TEST2.

wire aclk;
reg [2:0] a;
reg [2:0] b;

always @(posedge aclk)
begin

b = a+1;
a <= b;

end


I'm confused that TEST1 and TEST2. I think 2 above codes are working as the same, But I've got the different result of synthesis.

First is 6FFs and last thing is 3FFs,

So I'm confusing this.

• How is this different from the first case in your Question on Stack Overflow? The Answer there is perfectly fine. – Kevin Kruse Jan 14 at 13:52
• You asked that question before on stackoverflow and you received an answer. and the result is still the same: that is illegal code for synthesis and as such there is no correct answer. Your synthesis tool may generate registers, but in that case your hardware and simulation will not match. That is a big no-no I also don't see how you can run synthesis as there no inputs/outputs so all logic will be optimized away. – Oldfart Jan 14 at 13:53

When you use non-blocking assignments (<=) within a sequential block(@(posedge clk)), the variables you assign become flops. The order you read or write to the variable does not matter because you always read the old value of the variable.
When you use blocking assignments (=) within a sequential procedure, the order you perform read versus write matters in determining with the variable becomes a flop. If you read before write, the variable becomes a flop, otherwise it becomes combinational logic.
• In TEST1, b is read first, then the next statement b is written. So it becomes a flop. In TEST2, b is written first, then read, so no flop. In Both examples, a gets written with a non-blocking assignment, so order does not matter, and it becomes a flop. – dave_59 Jan 15 at 15:58