For example a NAND-gate with 3 inputs has 3 NMOS in series and 3 PMOS in parallel. But why aren't there cmos gates with e.g. 10 inputs?


More transistors in series means more effective resistance between the output pin and either ground (NMOS) or the power supply (PMOS). Since the load is capacitive, transition times are (to first order) proportional to the number of transistors in series.

Furthermore, transistors in a series string that are farthest from ground/power will see a significant negative voltage from source to body until the transistors closer to ground start conducting. This increases the transistor's threshold voltage, so it's harder to switch a bunch of series MOSFETs at the same time.

Actually, there are CMOS gates with 10 inputs or more but they are used only in special cases. Address decoders often have many inputs but they use precharged wired-OR types of logic.

  • \$\begingroup\$ You'll likely get imbalanced propagation delays. \$\endgroup\$ – analogsystemsrf Jan 17 at 3:19

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