I have some confusion regarding the guidelines for clearance between surface uncoated PCB traces (specifically component pads). IPC-2221 guidelines and other guidelines and standards indicate spacings that don't seem to make much sense.
I was intending to use a connector with 48V DC until I realized that it was rated for 30V maximum, on trying to figure out why this was I realized that the pads were at a 1.25mm pitch, which left less than 0.6mm between pads, thus violating the indications of IPC-2221. The connector pins themselves are spaced at 2.5mm leaving plenty of clearance otherwise.
These indications jump from 0.1mm for V<=30V to a minimum of 0.6mm for 30V < V < 150V (other standards indicate 0.4mm for V<50V, I have no access to EN 60664-1). Such jumps seem rather excessive.
I understand that air can withstand a field of 3kV/mm (i.e, 300V @ 0.1mm), so clearly this must be a surface contamination and creepage requirement more than a clearance requirement. Or perhaps it is also meant to take into account field increases due to 90° corners. But I even found a military test document that recommends as little as 0.13mm for 100V for altitudes of <3000ft.
I am pretty sure that many manufacturers go below the IPC recommendations (e.g., I am using a DC-DC converter rated for 60V input in a BGA package with a 1mm ball pitch and a maximum ball dimension of 0.7mm which leads to <0.3mm pcb spacing), the manufacturer does not even suggest using a sealer for the underside of the IC.
Besides subjecting the assembled board to (expensive) testing, is there any way to responsibly specify a smaller distance between traces?
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