# Circuit with two opamps

I have the following circuit: simulate this circuit – Schematic created using CircuitLab

I need to determine period of oscillations for the given circuit and to sketch waveforms of the voltages at nodes n1, n2 and n3.

Values of the resistances and capacitance are known and OPamps are considered to be ideal.

$$R_1=47k\Omega\\ R_2=39k\Omega \\ R_3=10k\Omega \\ C=100nF$$

Basically, what I can see here, is that this circuit consists of an inverting amplifier in series with an integrator (correct me if I am wrong), but I really cannot see the way to sketch the waveforms required since I cannot see what is actually going on here.

• hm, which one is the inverting amplifier? – Marcus Müller Jan 17 '19 at 16:24
• I suppose the first one, or it is the non inverting one, since we have the feedback to the positive input, i am bit confused now actually. – cdummie Jan 17 '19 at 16:32
• As @MarcusMüller is hinting, pay careful attention to your feedback polarity. What does that make the first circuit? – John D Jan 17 '19 at 16:32
• Well, positive feedback to the positive input, then it should be non-inverting amplifier, does that make any sense? – cdummie Jan 17 '19 at 16:34
• I've corrected your drawing for you. – Warren Hill Jan 17 '19 at 18:06

If the op-amps are to be considered as ideal, regenerative feedback will happen if both u1 and u2 are connected either both inverting, or both non-inverting

Here are a few clues to get you going. simulate this circuit – Schematic created using CircuitLab

Figure 1. OP's schematic with U1 inputs labelled. It's not shown here but the circuit needs a split-rail power supply to work. e.g., +/-12 V.

Consider that the circuit has just been powered up. If everything was ideal then the op-amp inputs and outputs would be at 0 V and nothing would happen. Fortunately for this circuit real op-amps aren't ideal and have slight differences in the input offset voltages and this is enough to kick the circuit into life.

I've shown U1's non-inverting input at +1 mV and the inverting input, n0, at 0 V.

• In that condition what will happen at n1?
• What that initial change happens at n1 what will the voltage be at U1's non-inverting input?
• Meanwhile what's happening to the voltage at n2? (Caution: trick question.)
• What's happening at n3?

Sketch that part out and post a photo into your question and we'll go from there.

Well, when the input reaches high enough level we will have logic zero at the output of the Schmitt trigger.

This suggests some slightly mixed up thinking.

1. This isn't a logic circuit - it's analog so while U1 can switch high or low they're not really 'logic' levels.
2. You are correct if you mean that the output switches low but what is low in this circuit? (I gave you a hint in the caption of Figure 1.)

Also, I think that same thing should happen in n2 since those points are separated only by a single resistor.

No, n2 is what's known as a 'virtual ground' due to the negative feedback caused by C1. R3 controls the current into the integrating capacitor. If the op-amp output is not in saturation then the output will adjust to maintain n3 at (or very, very close to) the voltage on the non-inverting input, 0 V. See How does an op amp integrator work? where this is currently under discussion.

• Well, the first part of the circuit is schmitt trigger, so it is generating a pulse train at its output (node n1) i expect the same waveform at node n2, but i cannot see what will happen with the waveform after integrator in this case – cdummie Jan 17 '19 at 21:43
• Schmitt trigger is correct but you haven't generated a pulse train yet. I have given you four questions. What is the answer to the first one? – Transistor Jan 17 '19 at 21:56
• Well, when the input reaches high enough level we will have logic zero at the output of the schmitt trigger – cdummie Jan 18 '19 at 6:28
• also, i think that same thing should happen in n2 since those points are separated only by a single resistor – cdummie Jan 18 '19 at 6:34
• See the update. – Transistor Jan 18 '19 at 8:19