Protecting analog pin from ESD strike

Question

After reading some relevant questions on ESD here, I have come up with the following approach to protect some ADC GPIO pins on my lipo battery operated board that are open to external input, thus being potential ESD targets.

I want to be able to protect against real world ESD events that could be upto 15kV or 20kV. These pins are 3.3V level, so I found found this ESD array chip that is rated to handle 30kV. It has a pF range capacitance, so that shouldn't be a problem.

I am not entirely sure how to handle the clamping voltage level. The data sheet says the DC breakdown voltage if 6.5V, which is definitely higher than the rated max on the chip. So even if the diode protects itself, my input could potentially be fried?

One of the ways to mitigate current due to high voltage I have seen is adding a series resistor after the diode stage which is usually in the sub 100ohm range. I am not sure of the math involved here in getting this resistance. I have seen notes suggesting resistance before and after the ESD diode stage. How do I decide? These two threads[one, two] provide conflicting suggestions

Answer 1

Don’t forget that most ICs already have ESD clamps on most of their pins, your objective should be to reduce the ESD event energy to a level that can be safely handled by the IC itself.

During an ESD event many parasitics, particularly PCB trace inductance and resistance, come into play. You can count on these to either make the problem worse or work in your favor.

Adding an explicit resistor between the ESD source and the clamp will improve the behavior of the clamp, this also applies to the IC pin clamps. Thus, by adding two resistors, one before the clamp and one after it, you considerably increase the energy handling at the pin. But in many cases this might be overkill, as the PCB trace impedance (after the clamp) might already provide enough protection and the added resistance could affect circuit behavior.

A more critical aspect might be the power-supply traces to the clamp itself. Using clamps with built-in zeners and a local bypass capacitor would improve energy handling more than a small series resistor would.

I would suggest looking at the IC pin model and put it in a simulator with a few PCB parasitics and apply a discharge model so you can get some intuition on where the energy is going.

Answer 2

THis works for me as a LPF and two stage clamp