After reading some relevant questions on ESD here, I have come up with the following approach to protect some ADC GPIO pins on my lipo battery operated board that are open to external input, thus being potential ESD targets.
I want to be able to protect against real world ESD events that could be upto 15kV or 20kV. These pins are 3.3V level, so I found found this ESD array chip that is rated to handle 30kV. It has a pF range capacitance, so that shouldn't be a problem.
I am not entirely sure how to handle the clamping voltage level. The data sheet says the DC breakdown voltage if 6.5V, which is definitely higher than the rated max on the chip. So even if the diode protects itself, my input could potentially be fried?
One of the ways to mitigate current due to high voltage I have seen is adding a series resistor after the diode stage which is usually in the sub 100ohm range. I am not sure of the math involved here in getting this resistance. I have seen notes suggesting resistance before and after the ESD diode stage. How do I decide? These two threads[one, two] provide conflicting suggestions