# Why does the PWM signals amplitude drop once connected to low-side n-mosfet switch?

I am applying a 3.3 V pwm signal to a circuit similar to the following (Credit: Olin Lathrop):

I am using an IRLR024N N-MOSFET, which switches if i connect the gate to the 3V3 pin of my microcontroller. It doesn't switch if i use the PWM signal though. The oscilloscope shows it clearly: The voltage difference between gate and source terminal is not great enough (from datasheet): $$V_{gate\_treshold\_max} = 2 V$$ Sorry for the bad image quality, 1V/div, math mode, ch1 (red) is the pwm pin, ch2 (yellow) is the ground pin, green is ch1-ch2. The first picture is without connection to the circuit in the first picture: Now when i connect the PWM-pin to the gate, ground pin to source of the mosfet (I have an 12V 5A Power supply which feeds the circuit): Do you have an idea what may be the issue or what could be a solution?

If you have any questions, i will answer ASAP!

Kind regards

Update: All good now, IRLU024N just wasn't up to the task. IRF3708 does the trick. Also fixed my measurements and used the ground clamp on the probes. I get around 7V@100% Duty-Cycle. I tested the circuit on a breadboard though. Next step is diagnosing where the rest of the voltage drops happen and then soldering to a PCB. Running into this problem and your answers helped me expand my understanding tremendously though, so thank you!

• what uC ? is this 3.3V logic? or 5V logic @ 3.3V you need at least a 1V MOSFET with 5Ω max or so. an intermediate driver using >=5V Vcc.on this added FET or a <1Vt FET Jan 18 '19 at 22:09
• You appear to have no ground connected to your scope. Jan 18 '19 at 23:33
• @SunnyskyguyEE75 NodeMCUv2 Jan 19 '19 at 7:13
• @JackCreasey I did this on porpuse, the oscilloscope cannot handle more than 50 V, and if i use the oscilloscope's ground I could have voltage differences up to 325V since I am measuring behind a buck converter (DC adapter for laptops) Jan 19 '19 at 7:17
• If your oscilloscope has a three pin AC plug and uses ground as it should you still have the potential difference. You have not accomplished anything by leaving off ground, other than distort your signals. Use a decent power supply (or even a battery) for development then you don't have to deal with this sort of issue. Jan 19 '19 at 16:48

Can you get at 3.3V with 50 Ohm gen using 3.3V no load? Your 3.3V signal looks like a 35 ohm load on 100 Ohms or ~1/2 of your driver impedance thus 1/(1+2)=1/3 the voltage

• clean up your measurement skills , so GND waveforms are a flat line with no noise and get textbook waveforms.
• your driver must be 0.65Ω to 6.5Ω depending on slew rate needed and 2~3x Vgs(th)

You cannot even conduct properly when the threshold for conduction Vt = VGS(th) Gate Threshold Voltage = 1 to 2V @ ID=250uA or RdsOn = 4kΩ to 2kΩ when you are expecting <0.1Ω

## my Rule of thumbs

• use gate drive voltage = 2 to 3 x Vgs(th) max or 4 to 6V as the Minimum Vgs and 15V max.
• use gate driver impedance = 10 to 100 x rated RdsOn = 0.065 Ω @ Vgs=10V
• your driver must be 0.65Ω to 6.5Ω depending on slew rate needed and 2~3x Vgs(th) - If switching slow, Driver ohms can be > 1000 RdsOn but not fast.
• although not in datasheet Rg internal resistance is also voltage dependant like RdsOn which is why I use these ratios.
• if you are using 5V logic @ 3.3V they have a driver RdsOn of 50 Ω +/-50%
• if you are using 3.3V logic @ 3.3V they have a driver RdsOn of 25 Ω +/-50%

Assuming 5V logic uC with 50 Ω and an output loaded to 1.1 to 1.2V, your apparent gate load a tad more than 1/3 of your driver resistance ~ 17 Ohms at this voltage which will probably drop to 8 Ω or so during switching edges only in series with Ciss which also changes with Vgs. See Q vs Vgs chart in your datasheet. fig 13a

• To be honest everything about impedance in your answer is to hard to swallow for me at once. I made the following calculation based on the fact that the NodeMCU can supply Imax = 12mA per port: Q = I * t = C * V => t_worst_case = C * V / I = 800pF * 3.3 V / 1mA = 2.64microSeconds (800pF is not in the datasheet), the goal frequency of my application would be 25khZ =^ 40microSeconds so the gate should be fully charged 13/15 of the time. Was this approximate calculation wrong? I will try to grasp every aspect of your answer over the weekend. Jan 19 '19 at 7:33
• ok What is Voh @12mA 3.3V-0.4V?? RdsOn=(Vcc-Voh)/Ioh = driver impedance for CMOS logic All ARMS are 3.3V logic (3.6max) chips and typically that is 25 Ohms , next CMOS rated for 5.5Vmax are 5V CMOS and they are all typ 50 Ohm drivers +/- worst case. If your supplies are not grounded to scope probe gnd, you get messy waves from floating supply noise Jan 19 '19 at 8:14
• You can test this tinyurl.com/yagq2xte and compare values to yours. Jan 19 '19 at 9:04
• Thank you for all of your input, will take a look at it in the evening! Jan 19 '19 at 9:54
• Disregard the Gate impedance ratios, that I suggested, if your application is not using the full switching power of the FET. I honestly can't for sure why your gate voltage dropped to 1.2V, unless there is a fault. If you load it with 50 Ohms only you can calc the driver impedance from the voltage drop or rise depending where it is terminated. But there are tolerances. ciao. Jan 19 '19 at 9:59