# Generate one-input pulse in Verilog

I'm attempting to port discrete schematics into a FPGA. In the schematics some AND gates function as short pulse generators, when input goes low output is enabled, until input propagates down an inverter chain and disables the gate (Similar to the answer described here.) Thus a short pulse is produced every negative edge. I'm new to Verilog, and am not sure of the best way to recreate this effect in Verilog. Would the code below work and is it a proper solution?

module pulser(input in,output out);
reg mem;
assign out = mem & !in;
always @(negedge in) begin
mem <= 0;
end
always @(posedge in) begin
mem <= 1;
end
endmodule

• Your two always blocks are essentially equivalent to assign mem = in;. Unfortunately timing of gates in FPGAs is not particularly predictable, and FPGA synthesis tools aren't designed to play the kind of trick that might have been used in the old discrete logic design. You'll probably have to use a substantially different approach to achieve the same overall function in an FPGA. (Hint: if you have a clock signal available, you almost certainly want to use it here. If you don't have one, you want to add one to your design) – The Photon Jan 19 '19 at 5:12
• As has been pointed out: you can not generate such a signal. I suggest you tell/show us the rest of the design especially where this 'runt' pulse is used. I have done a schematic to Verilog conversion for an new Zealand amateur satellite. There I also had to do make some major changes. – Oldfart Jan 19 '19 at 9:26
• Ok, I thought this wouldn't translate easily to a FPGA.I looked at the overall project and saw that the circuitry that the pulse circuit is part of runs at a fraction of the board's available clock. Would a valid solution be to make a clock-based pulse circuit which turns off after one cycle of the fast clock? – CatOnAKeyboard Jan 19 '19 at 20:28

You have mem driven in two always blocks and updated on both edges of in. That's not going to be synthesizable, and I'm doubtful that it is even legal Verilog. What you are trying to create is an asynchronous delay using combinational feedback. That's a hack. It's very difficult to control the placement and wiring of logic in an FPGA as you can with discrete gates, so even if you could describe it in Verilog the synthesizer would probably either optimize the delay away or tell you it is an invalid combinational logic block.