I'm attempting to port discrete schematics into a FPGA. In the schematics some AND gates function as short pulse generators, when input goes low output is enabled, until input propagates down an inverter chain and disables the gate (Similar to the answer described here.) Thus a short pulse is produced every negative edge. I'm new to Verilog, and am not sure of the best way to recreate this effect in Verilog. Would the code below work and is it a proper solution?
module pulser(input in,output out); reg mem; assign out = mem & !in; always @(negedge in) begin mem <= 0; end always @(posedge in) begin mem <= 1; end endmodule