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I am attempting to build my very own 8086 computer. (I know, awesome right?) But not to confuse you, this post focuses only on the 8284A. We have started to cover the Intel 8086 chip in my microprocessor class but unfortunately the class only covers textbook and Assembly stuff, not the actual hands on hardware.

I thought the systems clock would be a good place to start. After all without a good clock the processor is wasted. I purchased a handful of 8284As and a 15MHz crystal to use with the x1 and x2 outputs. I have put together my test circuit and it is shown below.

enter image description here

The wave output from the CLK pin looks like this:

enter image description here

Based on the datasheet for this chip the clk output is suppose to be 5Mhz with a 33% duty cycle. The output is extremely close to 5Mhz. The time division knob is set to .1us. The voltage is also consistent. However, it looks like the capacitors are discharging too soon. It's no where close to a square wave! My guess is bigger capacitors on the x1 pin. Any suggestions?

As always, thanks for your help.

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  • \$\begingroup\$ The datasheet link says "Your require pages is cannot open by blow" :-) \$\endgroup\$
    – stevenvh
    Commented Sep 20, 2012 at 17:19
  • \$\begingroup\$ @stevenvh Hahaha that's quite the error msg! I added a new link. Thanks for the heads up. \$\endgroup\$
    – atomSmasher
    Commented Sep 20, 2012 at 17:22
  • \$\begingroup\$ What's with the three caps at the left? Are they 1nF or 10 pF?? \$\endgroup\$
    – stevenvh
    Commented Sep 20, 2012 at 17:23
  • \$\begingroup\$ @stevenvh They are 10pF. I didn't even notice that! That's sloppy (and PSPICE) for you. I will fix this as well. \$\endgroup\$
    – atomSmasher
    Commented Sep 20, 2012 at 17:25
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    \$\begingroup\$ Seriously, you need to go back and fix all the typos in your part numbers. Are you really using the 8060 chip (a.k.a. SC/MP from National Semiconductor)? Or are you using the 8086, the Intel chip normally driven by an 8284 (not 8486 as shown in your schematic)? \$\endgroup\$
    – Dave Tweed
    Commented Sep 20, 2012 at 17:31

1 Answer 1

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The 100 pF load on the CLK signal shown in the data sheet is a test load used to verify worst-case timing. You don't need to have it in your circuit, and the waveform will probably look a lot better without it.

But actually, given that load, that waveform looks fine. Those old clock drivers didn't produce particularly "square" waves — and in fact, you wouldn't want them to, because it would just add to EMI and other bad effects. The key things are that the edges are monotonic (no glitches or "hooks" near the logic thresholds) and that the spacing of the crossings (about halfway between the peaks, third line down on the 'scope graticule) has the right timing (frequency and duty cycle), which it does.

BTW, your reset wiring is incorrect. R4, C5 and U1 should connect to the RES- pin, which is an input. The RESET pin is an output intended to drive the CPU's reset input.

Also, the PCLK pin is an output, and should not be tied to Vcc. Just leave it open if you're not using it.

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