I can't assign std_logic_vector to integer. What do I wrong?

signal data_out: std_logic_vector(20 downto 0);
signal d_value :  integer;

and in process

test: process(data_out)
        variable d_value_int : integer;
            d_value_int := to_integer(unsigned(data_out));
            d_value <= d_value_int;
    end process test;

I tried to do it like this, but it doesn't works too:

test: process(data_out)
        variable d_value_int : integer;
            d_value <= to_integer(unsigned(data_out));
    end process test;

Always my d_value isn't changed. It's 0 in simulator I used snipet from xilinx which send here Blair Fonville and it doesn't works with my example. I have some differences, coz my a here is signal and b is signal and my code is in process. That's differences


1 Answer 1


You haven’t given enough info: your snippet is incomplete (nowhere do you actually show that the value should be anything but 0), the error could be in your simulation, and I’m not sure why you’re using processes.

But ultimately, assuming you have added the appropriate library and packages, the function call is correct.

Check your code against this:

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

entity conv_test is
   Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
          b : out integer);
end conv_test;

architecture Behavioral of conv_test is


b <= to_integer(signed(a));

end Behavioral;

For unsigned integer, modify the snippet as:

b <= to_integer(unsigned(a));


  • \$\begingroup\$ I add USE IEEE.Std_logic_1164.all; USE IEEE.NUMERIC_STD.ALL; packages. Process is in architecture->begin->process. Other processes works, but this one doesn't. My value in data_out change, but this proces don't change data when I simulate code. I tried this snippet and it works so I did it simillar like here, but in process. My a here is signal and b is signal. That's difference too \$\endgroup\$
    – Noname
    Jan 20, 2019 at 6:06
  • \$\begingroup\$ @Noname But why is it in a process? This is not a sequential statement, it’s just a conversion. Move it outside the process block. \$\endgroup\$ Jan 20, 2019 at 6:15
  • \$\begingroup\$ I tried it to, but it doesn't works. I want change data here when data_out change value \$\endgroup\$
    – Noname
    Jan 20, 2019 at 6:16
  • \$\begingroup\$ @Noname are you assigning to d_value anywhere else in the simulation? If so, that’s the problem; if not, you need to post your full code. \$\endgroup\$ Jan 20, 2019 at 6:21
  • \$\begingroup\$ can I do it you on priv? It's study project and I think I shouldn't send it here before I send it to my teacher \$\endgroup\$
    – Noname
    Jan 20, 2019 at 6:22

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