1
\$\begingroup\$

I have the following circuit and I'd like to know about its stability :

enter image description here

From what I've learned from basic electronics courses, the first step is to add the parasitic capacitances. I know there is one from the gate to the source of the transistor. In this case, Cgs is from the gate to the ground since the source is connected to ground.

Now the capacitance from the gate to the drain Cgd gives me trouble. The gate and the drain are connected so is there any point in adding a capacitance somewhere? And even if I did, where would I place it in the circuit?

I can proceed by finding the poles later but I have to place the capacitances correctly first. If there is indeed no capacitance from gate to drain in this case, then we only have one pole given by $$\frac{1}{R_d(C_1+C_{gs})}$$

\$\endgroup\$
4
  • \$\begingroup\$ \$C_{gd}\$ is short-circuited, so you can ignore it as long as the wire connecting the drain and source isn't long enough to have significant inductive reactance at the frequency of interest. \$\endgroup\$ – Hearth Jan 20 '19 at 19:48
  • \$\begingroup\$ Great. So , I suppose there is only one pole to the system and that ensures its stability. Am I correct? \$\endgroup\$ – John Katsantas Jan 20 '19 at 19:51
  • \$\begingroup\$ Honestly, it's been too long since I've had to do any stability analysis, I'm going to let someone else answer that. \$\endgroup\$ – Hearth Jan 20 '19 at 19:52
  • \$\begingroup\$ If the gate-stripes are really long, there will be lots of time-delay along the (poly) gate stripes; delay is phaseshift is peaking-risk is oscillation-risk. Thus how you LAY OUT the transistor will matter. You can simulate this, using 5 or 10 FETS. I'll put this in an answer. \$\endgroup\$ – analogsystemsrf Jan 20 '19 at 21:45
2
\$\begingroup\$

Yes, such a circuit is always stable.

To make it oscillate you need to change the circuit such that more phase delay is introduced so by:

  • adding an inductor
  • adding a 2nd amplifier stage

If you analyze the small signal equivalent of this circuit you should find that it has only one pole and such systems are always stable.

Indeed C1 is in parallel with the Cgs of the NMOS.

If you want to evaluate the influence of Cgd (it's a Miller capacitance!) then analyze this circuit by drawing the small signal equivalent circuit and analyzing it.

\$\endgroup\$
4
  • \$\begingroup\$ Where would I place the Cgd capacitance since gate and drain are shorted? \$\endgroup\$ – John Katsantas Jan 20 '19 at 20:20
  • \$\begingroup\$ Where do you think it is? So what can you do when it is shorted? If you have no clue: suppose I have a capacitor in my hands. Now I sort it with a wire. Now if I measure this capacitor with a parallel wire, how does it behave? \$\endgroup\$ – Bimpelrekkie Jan 20 '19 at 20:22
  • \$\begingroup\$ Well, by its name it has to start at the gate and go to the drain. But the gate and the drain are at the same voltage. So I suppose we can ignore it. Otherwise it would be like connecting the two ports of a capacitor together. If it were a Miller capacitance we'd have to find the gain from the gate to the drain and then find the two equivalent capacitances from gate to ground and drain to ground using Miller's theorem. \$\endgroup\$ – John Katsantas Jan 20 '19 at 20:27
  • \$\begingroup\$ Even if we say that it's a Miller capacitance , the gain from the gate to the drain is 1. Applying Miller's theorem will then give 2 capacitors with zero capacitance. Ok, you made me think about it a little bit more and it makes sense now. Thanks! \$\endgroup\$ – John Katsantas Jan 20 '19 at 20:38
0
\$\begingroup\$

consider this, with delays and thus phase-shifts

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.