Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom vendor specific IP of the FPGA, that must be configured and placed in the design.
Is there a way around this? Can I program/define my own PLL in VHDL, that is preferably synthesized using the internal hard coded PLL blocks of the FPGA and works for Altera and Xilinx without having to manually insert the PLL to a project via MegaWizard & Cons?