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  • Here M1 and M2 are differential pairs with analog input. When source resistor is used Rs M1 and M2 when Vgs is less than 0.7 Vt threshold M1 and M2 will be in cut off region and Vo1 and Vo2 will be in Vdd potential .
  • But this is solved using current sink with specific value of current. Here to work in negative cycle M1 and M2 source potential is should go to negative according to the simulation it is and it should theoretical (i am not sure whether its negative).
  • When i replaced current sink with diode connected nmos transistor it didn't behave as current sink.
  • I have attached simulations Schematic using ideal current source and diodde connected current sink Here V003 is source potential of differential pair

  • But the question is how does this replacement of current sink solve the biasing of the mosfet problem and whats happening in that source potential

How is that source node behaving with resistor (Rs) common mode input and in differential mode input the M1 and M2 plus how does current sink solve the problem?

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If you are using enhancement-mode transistors, then the input transistor drains need to be below ground. A current source will do that; a FET (which can't generate voltages) cannot.

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