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I have a battery operated device with an old B&W LCD in it. I'm tapping to the display bus and would like to input it into an FPGA for some processing.

The bus includes vertical and horizontal sync. pulses, some pixel data and a clock at about 4 MHz. I connected the bus ground of the portable device to the FPGA dev. board ground using what I think is a good quality connection (soldered) and reassured under 1 Ohm using my handheld DMM.

To make things further complicated the data comes out of the device in 5V and I scale it down to 3.3V using a voltage divider (10K-20K).

When viewing the signal using a scope I can the signal is actually 1.7 Vppk + it does not "start" at 0 V but at about -0.5 V. The voltage can be explained by loading the bus because it has the original LCD hooked up + the FPGA + scope is parallel. However what's up with the signal being negative in part?

I need to come up with a way to buffer the signal to give it better drive capability. What comes to mind is some form of logic gates like inverters (2 in series) or something similar.

Does anyone has a better suggestion + an idea what is going on with the negative voltage?

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If this is an LCD display panel (like and old laptop), they are typically driven bit serial with LVDS driver chips (like the DS90CF563 http://www.ti.com/lit/ds/snls107e/snls107e.pdf ), or even current signalling - mostly because the LCD cable was the biggest RF radiator in the entire device.

If it's current signalled you may find that the input to the panel isn't just a resistor, but a current sink driven from a negative voltage.

You could use a line receiver (eg an SN75HVD12 http://www.ti.com/lit/ds/symlink/sn75hvd12.pdf ) which will drive your fpga directly and happily cope with all sorts of unpleasant voltages on the input.

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