Microprocessor 8085 regains control of the bus

Question

a) immediately after HOLD goes Low b) immediately after HOLD goes high c) after half clock cycle has passed once HLDS goes low d) after half clock cycle after HLDA goes high

This question was asked in GATE IN paper 2001. As per the answer key, the answer is B.

I think the answer is (a). The way I understand it, since HOLD pin in a 8085 is active high, once a peripheral device sends a high to the hold pin, 8085 relinquishes control over both the address and data buses in the next machine cycle. So not immediately. The 8085 uses the HLDA pin (active high) to indicate it's ready to relinquish control.

Now once the peripheral is done with it's work. It sends a LOW signal to the HOLD pin and the microprocessor IMMEDIATELY regains control of the buses. Anything wrong here?

Answer 1

Your assumption is very spot on. Both the HLDA and HOLD signals are part of the DMA (data memory access), which is able to write directly to memory without having the processor to get involved.

(I am unfortunately not able to track down the original source of this picture as there are many websites with this exact same diagram.)

The DMA transfer happens with these steps:

1. Signal from device queuing initiation for the DMA by requesting the processor.
2. The processor will complete its current cycle and will approve the request for the device.
3. The device then sends an acknowledgement basically saying, "Thank you! We will proceed now..."
4. The processor senses the acknowledgement and starts monitoring the DMA and makes sure nothing weird happens between the device and memory.
5. Once the process is finished between the device and memory, the device will tell the processor, "Hey, we're finished here!"
6. The processor will then receive this message and then it will proceed to whatever it was doing before this all started.

Basically what the HOLD does is that it prevent the processor from doing anything when the DMA process is taking place. Once the device tells the processor that it's all finished, the HOLD will be sent LOW to allow the processor to resume its activities.