a) immediately after HOLD goes Low b) immediately after HOLD goes high c) after half clock cycle has passed once HLDS goes low d) after half clock cycle after HLDA goes high
This question was asked in GATE IN paper 2001. As per the answer key, the answer is B.
I think the answer is (a). The way I understand it, since HOLD pin in a 8085 is active high, once a peripheral device sends a high to the hold pin, 8085 relinquishes control over both the address and data buses in the next machine cycle. So not immediately. The 8085 uses the HLDA pin (active high) to indicate it's ready to relinquish control.
Now once the peripheral is done with it's work. It sends a LOW signal to the HOLD pin and the microprocessor IMMEDIATELY regains control of the buses. Anything wrong here?