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a) immediately after HOLD goes Low b) immediately after HOLD goes high c) after half clock cycle has passed once HLDS goes low d) after half clock cycle after HLDA goes high

This question was asked in GATE IN paper 2001. As per the answer key, the answer is B.

I think the answer is (a). The way I understand it, since HOLD pin in a 8085 is active high, once a peripheral device sends a high to the hold pin, 8085 relinquishes control over both the address and data buses in the next machine cycle. So not immediately. The 8085 uses the HLDA pin (active high) to indicate it's ready to relinquish control.

Now once the peripheral is done with it's work. It sends a LOW signal to the HOLD pin and the microprocessor IMMEDIATELY regains control of the buses. Anything wrong here?

The question itself

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  • \$\begingroup\$ After what goes LOW or HIGH? What bus are we talking about here? Could you provide a link to your question? It looks like you were able to access this document. \$\endgroup\$ – user103380 Jan 22 '19 at 17:11
  • \$\begingroup\$ The question can be found here in Page 4 question number 1.25. By Bus I assume they are talking about both the Data and Address Bus. So the question is regarding when control is given back to the microprocessor, after the Hold Pin (Pin number 39 - page 3 of the datasheet has it) goes either high or low. options c and d are regarding pin 38 - HLDA \$\endgroup\$ – Aditya P Jan 22 '19 at 17:18
  • \$\begingroup\$ Your first link appears to be private. I looked at the home page of the website and yeah, there's no way for us to be able to see what you're talking about. Perhaps you can take a screen shot and edit your question and put the screenshot into your question. \$\endgroup\$ – user103380 Jan 23 '19 at 0:08
  • \$\begingroup\$ I'll do that. The question really does not have any more details. This link might work. Page 4 Question 1.25 \$\endgroup\$ – Aditya P Jan 23 '19 at 6:46
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Your assumption is very spot on. Both the HLDA and HOLD signals are part of the DMA (data memory access), which is able to write directly to memory without having the processor to get involved.

enter image description here

(I am unfortunately not able to track down the original source of this picture as there are many websites with this exact same diagram.)

The DMA transfer happens with these steps:

  1. Signal from device queuing initiation for the DMA by requesting the processor.
  2. The processor will complete its current cycle and will approve the request for the device.
  3. The device then sends an acknowledgement basically saying, "Thank you! We will proceed now..."
  4. The processor senses the acknowledgement and starts monitoring the DMA and makes sure nothing weird happens between the device and memory.
  5. Once the process is finished between the device and memory, the device will tell the processor, "Hey, we're finished here!"
  6. The processor will then receive this message and then it will proceed to whatever it was doing before this all started.

Basically what the HOLD does is that it prevent the processor from doing anything when the DMA process is taking place. Once the device tells the processor that it's all finished, the HOLD will be sent LOW to allow the processor to resume its activities.

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  • \$\begingroup\$ I've numbered your steps so that I can comment on them individually. 1. Yes, this is the assertion of HOLD. 2. This includes synchronizing the HOLD input to the internal clock, and then reaching the end of whatever cycle might be currently in progress. Then the CPU asserts HLDA. 3. No, the device simply starts doing bus cycles. 4. No, the CPU does not monitor the bus signals during DMA in any way. 5. This is the negation of HOLD. 6. The CPU must again synchronize HOLD to the internal clock, and then it negates HLDA and resumes its own bus cycles. \$\endgroup\$ – Dave Tweed Jan 7 at 13:16
  • \$\begingroup\$ Therefore, the correct answer is (C), because of the synchronization delay in step 6. \$\endgroup\$ – Dave Tweed Jan 7 at 13:16

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