This paper by Clifford Cummings goes into a detailed comparison of the advantages/disadvantages of a two always block (with a clocked block and a separate combinatorial block, "1-" on your list) compared to a single always block ("2-" on your list).
The main advantages of the two always block coding style are:
- fewer lines of code, especially for large state machines
- (less repetition)
- also generally smaller diffs for ECOs to fix bugs
- better timing/area
The main disadvantage is:
- your state machine code is now split over two always blocks, instead of being in just one place.
At first, it seems kind of counter-intuitive that the two-always-block style would have fewer lines of code, since it is split over two separate always blocks. The main reason is there is less repetition by having to specify the outputs of the current state only once. With the one-always-block coding style, the output assignments must be made for every transition arc to the state, leading to more repetition. (Also, it can be less intuitive to think "when I transition to this next state, the output values should be..." instead of "in this state, the output values should be").
Read the paper for a more detailed comparison (53 pages), including the code used for each FSM coding style. Some of the code is slightly dated (the paper is from 2003), and a lot more synthesizers now do support the constructs in section 10.0 "SystemVerilog enhancements" such as using enums for the states, and always_comb/always_ff.
With regards to the timing/area argument, a sufficiently advanced FSM synthesizer should give very similar timing/area for the different coding styles, although it might be easier for a synthesizer to infer a more efficient FSM implementation using the two-always-block style. This may be relevant for your example of an SDRAM controller, although I wouldn't personally consider it to be a deciding factor for how to code FSMs.
See also the question here for more advantages/disadvantages.