Suppose I have the following data set
FFDD FFF5 0006 0007 0007 FFFE FFFD
So far what I have studied is that verilog stored data in
twos complement form, if i take the example of first sample
FFDD verilog will stored it as
11111111........ and after the data is processed by my verilog code. it returns me a
very huge value which is not desirable.
if I have the following module what modification i have to made so that i can get the proper result
module asf (in,out,clk,rst,en); input [15:0] in; // the input will be data set input clk,rst,en; output wire [15:0] out;// output of the module wire [15:0] h1o,h2o,inh1,inh2,inh3;// output of another module which //can be used as input in this module . . . .