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Suppose I have the following data set

FFDD
FFF5
0006
0007
0007
FFFE
FFFD

So far what I have studied is that verilog stored data in twos complement form, if i take the example of first sample FFDD verilog will stored it as 11111111........ and after the data is processed by my verilog code. it returns me a very huge value which is not desirable. if I have the following module what modification i have to made so that i can get the proper result

 module asf (in,out,clk,rst,en);
    input [15:0] in; // the input will be data set
    input clk,rst,en;

    output wire [15:0] out;// output of the module
    wire [15:0] h1o,h2o,inh1,inh2,inh3;// output of another module which //can be used as input in this module
.
.
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    \$\begingroup\$ You'll need to share the actual calculation you're doing if you want us to advise you how to make it work with 2's complement input. \$\endgroup\$
    – The Photon
    Jan 23, 2019 at 3:17
  • \$\begingroup\$ in addition to the below answers, you may want to take a look at this: stackoverflow.com/questions/24162329/… \$\endgroup\$
    – CapnJJ
    Jan 23, 2019 at 18:04

2 Answers 2

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Proper use of the new signed capability in Verilog 2001 can be summarized by a few basic rules.

  • Investigate fully all signed to unsigned conversion occurs. (VER-318) synthesis warnings. These point to incorrect functionality

  • All signed operands will be signed extended to match the size of the largest signed operand.

  • Type casting using $unsigned will make the operation unsigned. The
    operand will be sign extended with 0’s if necessary.

  • Type casting using $signed make the operand signed. The operand will be sign extended with 1’s if necessary.

  • Pad the operand with a single 0 before the cast if this is not
    desired. Expression type depends only on the operands or operation,
    it does not depend of the LHS of the expression

Reference : http://www.tumbush.com/published_papers/Tumbush%20DVCon%2005.pdf

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Verilog stores data in the same way that all digital computers do...as ones and zeros. 0xFFDD gets stored as 0b1111111111011101 because that is the exact equivalent binary representation for the hexadecimal literal. They are the same thing.

It's not clear why a "huge" value is undesirable to you, or what you think is the "proper result", but I'm going to guess that you want to see a negative value rather than a large positive value.

Whether these ones and zeros represent a large positive value or a negative value depends on how you chose to interpret them. You could declare these values to be signed values, and then your Verilog tools would interpret them as negative values.

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  • \$\begingroup\$ thank you, I almost got it, but when I am writing signed (0b1111111111011101) it is only taking the first bit as a sign bit but for my case it should be (FFDD=-DD=-11011101). so how can I get it? \$\endgroup\$
    – David
    Jan 24, 2019 at 10:02
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    \$\begingroup\$ Signed values use two's complement representation. Calling the MSB the "sign bit" is confusing, because the sign-magnitude representation also uses the MSB for the sign bit. Do some searching for "two's complement"...it is very well documented. \$\endgroup\$ Jan 24, 2019 at 12:49

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