Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
I am going through the book "Elements of computing systems". This book teaches how to build a whole computer from scratch. While I was just browsing the chapters on computer architecture, I noticed that it all focused on the Von Neumann architecture. I was just curious as to what are the other architectures and when & where they are used.
I know about only two, one is Von Neumann and the second is Harvard. Also I know about RISC which is used in uC of AVR.
There are many different kinds of computer architectures.
One way of categorizing computer architectures is by number of instructions executed per clock. Many computing machines read one instruction at a time and execute it (or they put a lot of effort into acting as if they do that, even if internally they do fancy superscalar and out-of-order stuff). I call such machines "von Neumann" machines, because all of them have a von Neumann bottleneck. Such machines include CISC, RISC, MISC, TTA, and DSP architectures. Such machines include accumulator machines, register machines, and stack machines. Other machines read and execute several instructions at a time (VLIW, super-scalar), which break the one-instruction-per-clock limit, but still hit the von Neumann bottleneck at some slightly larger number of instructions-per-clock. Yet other machines are not limited by the von Neumann bottleneck, because they pre-load all their operations once at power-up and then process data with no further instructions. Such non-Von-Neumann machines include dataflow architectures, such as systolic architectures and cellular automata, often implemented with FPGAs, and the NON-VON supercomputer.
Another way of categorizing computer architectures is by the connection(s) between the CPU and memory. Some machines have a unified memory, such that a single address corresponds to a single place in memory, and when that memory is RAM, one can use that address to read and write data, or load that address into the program counter to execute code. I call these machines Princeton machines. Other machines have several separate memory spaces, such that the program counter always refers to "program memory" no matter what address is loaded into it, and normal reads and writes always go to "data memory", which is a separate location usually containing different information even when the bits of the data address happen to be identical to the bits of the program memory address. Those machines are "pure Harvard" or "modified Harvard" machines. Most DSPs have 3 separate memory areas -- the X ram, the Y ram, and the program memory. The DSP, Princeton, and 2-memory Harvard machines are three different kinds of von Neumann machines. A few machines take advantage of the extremely wide connection between memory and computation that is possible when they are both on the same chip -- computational ram or iRAM or CAM RAM -- which can be seen as a kind of non-von Neumann machine.
A few people use a narrow definition of "von Neumann machine" that does not include Harvard machines. If you are one of those people, then what term would you use for the more general concept of "a machine that has a von Neumann bottleneck", which includes both Harvard and Princeton machines, and excludes NON-VON?
Most embedded systems use Harvard architecture. A few CPUs are "pure Harvard", which is perhaps the simplest arrangement to build in hardware: the address bus to the read-only program memory is exclusively is connected to the program counter, such as many early Microchip PICmicros. Some modified Harvard machines, in addition, also put constants in program memory, which can be read with a special "read constant data from program memory" instruction (different from the "read from data memory" instruction). The software running in the above kinds of Harvard machines cannot change the program memory, which is effectively ROM to that software. Some embedded systems are "self-programmable", typically with program memory in flash memory and a special "erase block of flash memory" instruction and a special "write block of flash memory" instruction (different from the normal "write to data memory" instruction), in addition to the "read data from program memory" instruction. Several more recent Microchip PICmicros and Atmel AVRs are self-programmable modified Harvard machines.
Another way to categorize CPUs is by their clock. Most computers are synchronous -- they have a single global clock. A few CPUs are asynchronous -- they don't have a clock -- including the ILLIAC I and ILLIAC II, which at one time were the fastest supercomputers on earth.
Please help improve the description of all kinds of computer architectures at http://en.wikibooks.org/wiki/Microprocessor_Design/Computer_Architecture .
CISC is the "opposite" of RISC. Whereas RISC prefers to have simple instructions that are easy for the compiler to optimize and often the same size, CISC is fond of complex instructions of varying size.
For instance, a pop instruction in CISC will modify the stack pointer and place the data from the stack into another register. However, a RISC processor would read the data with one instruction and then modify the stack pointer with a second instruction. (generally; there are some exceptions, like the PowerPC which can update the stack pointer and push data onto the stack, but that's an exception)
Since RISC instructions are all the same size, disassemblers are easier to write. Designing the processor is also easier, because the pipeline doesn't have to account for varying instruction sizes. However, CISC code density tends to be better, both because the complex instructions require fewer bytes to represent the same number of operations, and because the variable instruction length allows for some "compression".
There are also other exotic architectures, like VLIW/EPIC. This sort of architecture was designed with parallel processing in mind. However, they didn't do very well, because they place a very heavy burden on the compiler to optimize, whereas other architectures have fancy instruction windows that relieve some optimization burden from the compiler.
Both von Neumann and Harvard architectures can be used with RISC processors such as the AVR and ARM. The AVR uses Harvard, whereas some ARM chips use von Neumann and some use Harvard.
Well, there is something like the ENIAC, where you have essentially individual ALUs and you "programmed" them by wiring the output of one alu to the input of another alu that was going to perform the next operation on that intermediate variable. Your "registers" and storage are the wires connecting the alus.
I recently purchased the book "The First Computers--History and Architectures (History of Computing)", which in part focuses on this exact topic. I do not recommend purchasing this book though it is just a collection of academic papers, hard to read and I suspect probably published (for free) elsewhere. (I gave up on it before finishing the introduction)
Once memory was invented and became practical, we kinda settled into the two popular ones Von Neumann and Harvard. Executing from re-wiring, punch cards, paper tape or things like that became less practical. And there is stack based (the zpu for example), which I suspect probably falls under the Harvard category and not its own.
What about von neumann platforms that boot off of a read-only (in normal use) flash on one memory interface and have read/write data ram in another (that can sometimes operate on both in parallel) but from the programs perspective are in one address space? Or ones that have several internal and external memories/interfaces all operating in parallel but are von neumann for being in the same address space.
And what good is a harvard platform where the processor cannot access the instruction memory as data in order to change/upgrade the bootloader or for the bootloader to load the next program to run? Why isnt that a von neumann architecture? The processor executing from and operating on the same memory on the same interface in likely a sequential (instruction fetches and memory writes not happening at the same time) manner?
The two popular memory based architectures are more close than they are different in current implementations IMO.
Where do gpu's fall? Or the business that I work in, network processors (NPUs). Where you have these relatively small special purpose microengines (processors) that execute from a harvard like program ram (addressable but you just dont want to do that for performance reasons), operate on various data rams each having their own separate address space (separate processor instructions for each space), (the memory spaces operating in parallel) and through those rams hand off intermediate data to have the next computation done by the next microengine in a wired alu (eniac) like fashion? What would you call that one? Are npus and gpus just fancy modified harvard architectures?
