Circuit requirements:

  • DC voltage gain: 50dB
  • Unity gain bandwidth: 50MHz
  • Phase margin: 45 deg(60 deg is recommended).

enter image description here

The circuit is completely symmetric, so M1=M2, M3=M4, and M5=M6. Therefore the DC gain of the first stage without the buffer is

\$A_{V_o}=-g_{m_1}R_{out}, \ R_{out}=\frac{1}{1/r_{o_1}+1/r_{o_3}+1/r_{o_5}+g_{m_5}-g_{m_3}}\$.

Since we need a relatively high DC gain I can choose \$g_{m_5}=g_{m_3}\$ to make \$R_{out}\$ maximum. So \$R_{out}\$ becomes \$R_{out}=r_{o_1}||r_{o_3}||r_{o_5}\$.

From now on let's follow two different approaches in order to satisfy the above requirements.

Approach 1:

The circuit without the source follower M7 and the compensation network.

In this case the load capacitor, CL(=10pF), is directly connected to the drain of M2. Let's first try to find an equation for the unity gain frequency, \$f_u\$. The circuit has two poles with the dominant pole situated at the output node. If we assume that the next dominant pole is located far from the dominant pole, the transfer function can be approximated as

\$H(s)=\frac{A_{V_o}}{1+s/\omega_{p_1}}, \ \omega_{p_1}=\frac{1}{C_LR_{out}}\$

Since \$|H(j2\pi f_u)|=1\$, the equation for \$f_u\$ becomes roughly

\$f_u= \frac{g_{m_1}}{2\pi C_L}\$.

With \$f_u\$=50MHz, \$C_L\$=10pF, the above equation gives 3.14mA/V for \$g_{m_1}\$ (Neglecting parasitic capacitances). So that's for \$g_{m_1}\$.

Now with the \$g_{m_1}\$ already determined and the DC gain 50dB (or equivalently ~320V/V), it's just left to figure out \$R_{out}\$, which, as per equation for DC gain, should be ~100kohms. So I can easily modify \$r_{o_1}\$,\$r_{o_3}\$, and \$r_{o_5}\$ in order to make the parallel combination of them 100kohms. That's for \$R_{out}\$.

Phase margin is 90 deg since the other high frequency pole doesn't affect the phase margin. A 90-deg PM doesn't have ringing and overshooting but trades off speed. But I think that's fine.

So it seems that the first approach did work well without the need for the source follower and the compensation network.

Approach 2

The complete circuit.

Here comes my confusion. I do not know as to why we need to consider those added parts while approach 1 worked out fine. Could anyone please explain as to how the second approach can be better than the first (if it's better at all)?

I think compensation is only required if the phase margin's dropped less than 45 as the result of subsequent stages, or if we want good unity gain bandwidth (?). But I do not see any good reason to invoke compensation in the above circuit.

  • \$\begingroup\$ And what if a real load were connected? \$\endgroup\$
    – Andy aka
    Jan 24, 2019 at 13:01

3 Answers 3


Good question! Your DC analysis is correct, but your AC analysis lacks the frequency effects associated with M1, M2, M3 and M4, including those due to the reverse transfer capacitance. The phase shift associated with these will vary depending upon which FETs are chosen, but at some frequency your phase margin will be degraded to the place where the circuit will oscillate. The compensation circuit will roll off the gain before you reach this frequency.

  • \$\begingroup\$ Each line of your answer is a question for me! I am not sure what you mean by reverse transfer capacitance. The parasitic capacitance seen at the output node due to M2, M3, M4, and M5 is less than 1pF which is negligible compared to CL. Please elaborate on more by giving formulas and examples so I can understand what you mean. \$\endgroup\$
    – dirac16
    Jan 24, 2019 at 21:21
  • \$\begingroup\$ Reverse Transfer capacitance, also called Crss, is the internal MOSFET capacitance between gate and drain, which is often in hundreds of pF. There are other parameters Ciss (input capacitance), Coss (output capacitance) which are described in onsemi.com/pub/Collateral/AN-9010.pdf.pdf from Fairchild and many other app notes. These will provide phase shift at M3 and M4 such that an oscillation or ring-down can occur at a sufficiently high frequency. \$\endgroup\$ Jan 24, 2019 at 22:14
  • \$\begingroup\$ Oh you meant Cgd, but again these have no effect in the frequency band 50MHz? For a chosen WL the gate-drain capacitance of M3 or M4 is only a few fF and will be important only in sub GHz range \$\endgroup\$
    – dirac16
    Jan 25, 2019 at 10:06
  • \$\begingroup\$ Which MOSFET are you using? \$\endgroup\$ Jan 25, 2019 at 14:13
  • 1
    \$\begingroup\$ I think the inclusion of buffer helps prevent both the f-3dB and the unity gain frequency from dramatically decreasing due to a large capacitive load. The buffer prevents this while reducing the phase margin. Hence the need for compensation \$\endgroup\$
    – dirac16
    Jan 25, 2019 at 15:25

Why is frequency compensation required here?

Theoretically this compensation is not required. However, general practice of application of operational amplifiers has come to necessity of internal "compensation", which is essentially an intentional screw-up of an amplifier. This is done in industry for half a century now, to reduce instabilities in closed feedback applications. The detailed explanation of reasons can be found in every textbook and in this TI white paper, which says in part:

Op amps are internally compensated to save external components and to enable their use by less knowledgeable people. It takes some measure of analog knowledge to compensate an analog circuit. Internally compensated op amps normally are stable when they are used in accordance with the applications instructions. Internally compensated op amps are not unconditionally stable. They are multiple pole systems, but they are internally compensated such that they appear as a single pole system over much of the frequency range.


Approach 1 is good to drive capacitance loads, however if you drive resistive load it will reduce the output impedance of the amplifier and hence the gain.

Approach 2 has the source follower which acts as a buffer and you can drive both capacitive and resistive loads with the gain being the same.


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