SPI: effective payload throughput per clock tick?

Question

Let's say I'm clocking a SPI bus at 30 MHz.

What payload throughput can I actually expect? 30 Mbps, or less?

(E.g. are high overheads imposed by pauses, control packets, packet headers, packet checksums, etc? SPI noob here.)

Answer 1

SPI only defines a very small part of your protocol: just how a basic data word is transmitted and received. A data word will often be a byte, but that's not a requirement; if you want to define your SPI words as 19-bit you can freely do so.

How those 19 bits are defined is not part of the SPI specification, SPI just transmits 1 bit per clock tick, and doesn't care if that bit is part of your payload, preamble, CRC checksum, address, or whatever. So without further information on your word encoding it's impossible to say how high your payload throughput is.

If you use SPI to interface to a simple shift register your payload throughput will be 30 Mbps. If you want to interface with an EEPROM it will be less, since apart from your actual data you'll also have to provide the EEPROM address, and for byte mode writes payload throughput may be as low as 10 Mbps.

Answer 2

Wikipedia states the following:

• No in-band addressing
• No error-checking protocol

So no overhead there.

Also, SPI is completely non-standardized; e.g. different chips use different word lengths, or even use variable word lengths!

So it seems like averaging 1 payload bit / clock tick is theoretically possible, but in practice different slaves may or may not be able to do something useful with that many Mbps, and may enforce their own time delays between words.