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I've been brushing up on my analog design, and have some questions regarding improving the design of a simple comparator. It's been a while since I got this deep into it. I'm trying to implement it based around a differential amplifier.

I've been experimenting with how the different parameters affect the output of the system. I realize I could improve the performance using FETs instead, however I want to do this exercise with BJTs for the added challenge. I do also realize that the ideal components here don't take into account real world variations between parts which would require other steps to correct. I'm using a norton equivalent for the non-ideal current source at the emitters. I chose the parallel resistance somewhat empirically.

main schematic

I have a couple of questions to start with.

  1. I'm wondering how I can best go about increasing the input impedance. Doing a darlington array seems like the most common solution for this, however that does degrade the input bandwidth, and requires a larger signal. Is this an unavoidable tradeoff or are there methods I can use to achieve higher input impedance without degrading frequency response?

  2. I'm wondering how to manage the tradeoff between the emitter bias level, and the transition range (Not sure about the proper term for that). Sweeping a range from 0-40mA in 10mA steps, the output range increases, at the cost of a much larger input response being required to adequately drive the output to its full level. This plot is only showing the output of VOut2. emitter current bias sweep The 0mA and 10mA currents have fairly acceptable behavior. I know this is going to require some output conditioning to achieve a 0-VCC response, however I was wondering if there's anything else to be done with the differential amplifier that could improve this. I'm also considering adding in emitter degeneration resistors to see how that improves the input response.

  3. In another experiment, I held IBias constant at 10mA, and swept the reference voltage from 0-5V in 1V increments. As the reference voltage increases the output signal at VOut2 winds up being compressed further and further until it practically vanishes. What can I do with the input signals before they reach the differential amplifier to help correct this behavior?

  4. The output has when measuring between VOut2 and VOut1 is very nonlinear. This plot shows the output with the reference voltage stepped from 0-5V in 1V increments. List item The nicer stepped behavior only occurs when the reference signal is up at 5V. I'm wondering how I can go about improving this. The book I have describes emitter degradation as one method for widening the linear range, but what I'm seeing in this plot just seems excessively bad. VOut2 shows much nicer behavior, for a comparator application should I just be using that alone? This plot shows VOut2 with VRef being stepped as before: VOut2 response.

I'm working with Bipolar and MOS Analog Integrated Circuit Design by Alan Grebene, I would appreciate any other useful references I could look up.

Thanks!

EDIT: Plot of Q1 base current and collector current with swept reference levels: enter image description here

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  • \$\begingroup\$ Using FETs for the input stage is a common way to increase input impedance of op amps, and I see no reason you couldn't do it for a comparator too. \$\endgroup\$ – Hearth Jan 25 at 0:57
  • \$\begingroup\$ True, I wanted to try doing this design with BJTs just for the challenge. Once I've had my fun/learning with it I'm going to move onto a FET based design. \$\endgroup\$ – alphasierra Jan 25 at 1:08
  • \$\begingroup\$ Is this to be built with real parts from a bag or reel? Or are you going to just use Spice and perfect, identical parts at an exact temperature? \$\endgroup\$ – jonk Jan 25 at 1:54
  • \$\begingroup\$ This is just spice experimentation for my own learning. I know that using differences in real world components and temperature would change the behavior significantly. The textbook I mentioned shows some techniques for correcting for component differences. \$\endgroup\$ – alphasierra Jan 25 at 1:59
  • \$\begingroup\$ The typical early voltage of a small signal transistor is 100V, so you can set R1 to be 100/ibias. Many of your simulations result in saturating an element in the differential pair. If you plot the base current you may gain a better understanding of what's happening. \$\endgroup\$ – sstobbe Jan 25 at 4:32
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You may learn more by analyzing the best

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  • \$\begingroup\$ I wonder what the specifications of the transistors are. I imagine for the output stage it would be desirable to have something with a smaller early voltage? \$\endgroup\$ – alphasierra Jan 28 at 2:59
  • \$\begingroup\$ No just the opposite to reduce Rce leakage \$\endgroup\$ – Sunnyskyguy EE75 Jan 28 at 3:13

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