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schematic

simulate this circuit – Schematic created using CircuitLab

In the circuit above, what is R2 doing? I've not seen this before. The only thing I can think is it is current limiting for D1 if there were some transient backfed from Vout.

Ideas?

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  • \$\begingroup\$ What is this circuit from? \$\endgroup\$ – Hearth Jan 25 at 22:44
  • \$\begingroup\$ It's the output stage of a PWM to voltage converter -> D2A. \$\endgroup\$ – Aaron Jan 25 at 22:49
  • \$\begingroup\$ It actually slows down rise time into a large Ciss FET PWM switch since RdsOn in CMOS OA is 60 Ohms so the output during switching is now 110 Ohms But Av=2 What's it for? a 50 Ohm Line driver with 110 Ohms during switching? >>? C1 makes it even slower than 10V/us so it can't be for RF impedance match.. ... dubious design .. Perhaps for DAC noise reduction with an analog output and a limited output range on a capacitive load \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 25 at 23:26
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    \$\begingroup\$ Most likely for capacitive load isolation. ti.com/lit/ug/tidu032c/tidu032c.pdf \$\endgroup\$ – sstobbe Jan 25 at 23:45
  • \$\begingroup\$ @sstobbe Can you make that an answer, and I'll select it. \$\endgroup\$ – Aaron Jan 26 at 0:59
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Op Amps driving switched voltages with low impedance output and a capacitance load causes a loss in phase margin and oscillations. Adding addition Miller capacitance with a series R outside that loop improves the phase margin at unity gain so the output has a clean square wave.

To demonstrate this I modelled the OPA2172 CMOS RRIO OP AMP with 60 ohms output is in the datasheet. Without the C1 it oscillates even with the series R and dummy load capacitance.

The Zener prevents the load capacitance ringing from back driving the CMOS output above the supply rail which could cause shoot-thru failure.

enter image description here

Adding 50 ohms in series to a load cap before negative feedback is the not fix, unless there is ALSO some > 1pF negative feedback from stray capacitance.

This means if there was stray capacitance to the +ve input, it could still oscillate (IF IT did not have the shunt load cap on Vin+ which also LPF's the input)

Zout is the open loop output resistance given in the datasheet of 60 ohms.

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  • \$\begingroup\$ As @sstobbe commented, I think it's mostly to do with capacitive load isolation, which you also touch on. Thanks for the answer! \$\endgroup\$ – Aaron Jan 28 at 17:58
  • \$\begingroup\$ Adding 50 Ohms in series to a load cap before negative feedback is the not enough fix, unless there is ALSO some > 1pF negative feedback from stray capacitance. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 28 at 18:20
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It's matching the opamp output to a 50 ohm transmission line, which hasn't been shown.

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  • \$\begingroup\$ Wouldn't that then put R3 directly in parallel with C1? The output is slow moving DC levels, no transmission lines needed, nor used. They use bell wire, sometimes twisted, over a distances of tens of feet. \$\endgroup\$ – Aaron Jan 25 at 23:09
  • \$\begingroup\$ Re-stating, if it were simply matching the line impedance, wouldn't it be better to place R2 on the output, and not be included in the feedback? \$\endgroup\$ – Aaron Jan 25 at 23:11
  • \$\begingroup\$ If the line were correctly terminated, the the output would be halved, placing the feedback on the side of the resistor as shown fixes that. (it sounds like (bell wire, etc.) there's more context than you've given us. \$\endgroup\$ – james Jan 25 at 23:12
  • \$\begingroup\$ For the record, I think @Sunnyskyguy is right too - the resistor keeps the op-amp stable. \$\endgroup\$ – james Jan 26 at 11:28
  • \$\begingroup\$ Yes there are all multiple good and correct answers. The best one I think has to do with capacitance load isolation. But currently that is only in a comment. \$\endgroup\$ – Aaron Jan 26 at 19:27
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PWM to voltage, output stage - that's a buffered RC lowpass filter, buffer has quite precise voltage gain = 2 and the loss in R2 is compensated by taking the feedback from Vout.

R2 and the zener diode are inserted to protect the opamp in case one connects to Vout something which has a voltage, for ex. a charged capacitor. Consider R2 and D1 as an opamp ruggerization attempt.

So, you were right.

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Just another perspective.

I have no idea what the specs are for this circuit or even if this design is any good.

R2 has an effect of:

  • attenuating back EMF from a reactive load as a reverse LPF with feedback cap C1
  • more current limit in addition to the internal 60 Ohms
  • more phase margin for driving capacitive loads with a step response.

Lets' look at the transfer functions of the linear parts using the Zo=60 Ohms of the CMOS Op Amp,

enter image description here

  • The top shows a LPF at 162 Hz applied to the input.

  • The bottom shows a HPF at 330 Hz @-3dB from an output with Z= 1 Ohm

  • the breakpoint of your C1*(R3//R4)=T is thus amplified by the attenuation of the attenuation which I created by a series resistance. This effectively becomes a capacitance multiplier for shunting BackEMF noise and increasing the T value by the 50/1 for a step load pulse.

Just another perspective.

Here raising the load impedance shifts the HPF breakpoint to attenuate LF noise back on the source for other outputs while the input still has a DC gain of 2. enter image description here

So adding R2 flattens the BEMF response or s21 transfer function with a larger T value of LPF which in negative feedback becomes a HPF for s21 transfer function.

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